component
CD4081BPWR
Public Made by Adomby adom
Texas Instruments Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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page.json+17−14@@ -52,37 +52,37 @@ "number": "1", "name": "A", "type": "input",- "description": "Input A of gate 1 (2-input AND); accepts VIL \u2264 1 V / VIH \u2265 4 V at VDD = 5 V."+ "description": "Input A of gate 1 (2-input AND); accepts VIL ≤ 1 V / VIH ≥ 4 V at VDD = 5 V." }, { "number": "2", "name": "B", "type": "input",- "description": "Input B of gate 1 (2-input AND); accepts VIL \u2264 1 V / VIH \u2265 4 V at VDD = 5 V."+ "description": "Input B of gate 1 (2-input AND); accepts VIL ≤ 1 V / VIH ≥ 4 V at VDD = 5 V." }, { "number": "3", "name": "J", "type": "output",- "description": "Output of gate 1; J = A\u00b7B; output low-level VOL min 0 V, high-level VOH max VDD at VDD = 5 V."+ "description": "Output of gate 1; J = A·B; output low-level VOL min 0 V, high-level VOH max VDD at VDD = 5 V." }, { "number": "4", "name": "K", "type": "output",- "description": "Output of gate 2; K = C\u00b7D; output low-level VOL min 0 V, high-level VOH max VDD at VDD = 5 V."+ "description": "Output of gate 2; K = C·D; output low-level VOL min 0 V, high-level VOH max VDD at VDD = 5 V." }, { "number": "5", "name": "C", "type": "input",- "description": "Input C of gate 2 (2-input AND); accepts VIL \u2264 1 V / VIH \u2265 4 V at VDD = 5 V."+ "description": "Input C of gate 2 (2-input AND); accepts VIL ≤ 1 V / VIH ≥ 4 V at VDD = 5 V." }, { "number": "6", "name": "D", "type": "input",- "description": "Input D of gate 2 (2-input AND); accepts VIL \u2264 1 V / VIH \u2265 4 V at VDD = 5 V."+ "description": "Input D of gate 2 (2-input AND); accepts VIL ≤ 1 V / VIH ≥ 4 V at VDD = 5 V." }, { "number": "7",@@ -94,43 +94,43 @@ "number": "8", "name": "E", "type": "input",- "description": "Input E of gate 3 (2-input AND); accepts VIL \u2264 1 V / VIH \u2265 4 V at VDD = 5 V."+ "description": "Input E of gate 3 (2-input AND); accepts VIL ≤ 1 V / VIH ≥ 4 V at VDD = 5 V." }, { "number": "9", "name": "F", "type": "input",- "description": "Input F of gate 3 (2-input AND); accepts VIL \u2264 1 V / VIH \u2265 4 V at VDD = 5 V."+ "description": "Input F of gate 3 (2-input AND); accepts VIL ≤ 1 V / VIH ≥ 4 V at VDD = 5 V." }, { "number": "10", "name": "L", "type": "output",- "description": "Output of gate 3; L = E\u00b7F; output low-level VOL min 0 V, high-level VOH max VDD at VDD = 5 V."+ "description": "Output of gate 3; L = E·F; output low-level VOL min 0 V, high-level VOH max VDD at VDD = 5 V." }, { "number": "11", "name": "M", "type": "output",- "description": "Output of gate 4; M = G\u00b7H; output low-level VOL min 0 V, high-level VOH max VDD at VDD = 5 V."+ "description": "Output of gate 4; M = G·H; output low-level VOL min 0 V, high-level VOH max VDD at VDD = 5 V." }, { "number": "12", "name": "G", "type": "input",- "description": "Input G of gate 4 (2-input AND); accepts VIL \u2264 1 V / VIH \u2265 4 V at VDD = 5 V."+ "description": "Input G of gate 4 (2-input AND); accepts VIL ≤ 1 V / VIH ≥ 4 V at VDD = 5 V." }, { "number": "13", "name": "H", "type": "input",- "description": "Input H of gate 4 (2-input AND); accepts VIL \u2264 1 V / VIH \u2265 4 V at VDD = 5 V."+ "description": "Input H of gate 4 (2-input AND); accepts VIL ≤ 1 V / VIH ≥ 4 V at VDD = 5 V." }, { "number": "14", "name": "VDD", "type": "power_in",- "description": "Positive supply; operating range 3 V to 18 V; quiescent current 1 \u00b5A typ at 20 V."+ "description": "Positive supply; operating range 3 V to 18 V; quiescent current 1 µA typ at 20 V." } ], "provenance": {@@ -210,5 +210,8 @@ "docs/cd4081bpwr-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ]+ ],+ "visibility": {+ "public": true+ } }