component
CD4078BM96
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+50@@ -0,0 +1,50 @@+# CD4078BM96++**Texas Instruments** · Logic Gates · SOIC-14++CD4078BM96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | K | output | OR-gate output, K = A+B+C+D+E+F+G+H (non-inverted OR of all eight inputs). |+| 2 | A | input | Input A to the 8-input NOR/OR gate; protected by internal CMOS protection network. |+| 3 | B | input | Input B to the 8-input NOR/OR gate; protected by internal CMOS protection network. |+| 4 | C | input | Input C to the 8-input NOR/OR gate; protected by internal CMOS protection network. |+| 5 | D | input | Input D to the 8-input NOR/OR gate; protected by internal CMOS protection network. |+| 6 | NC | unconnected | No internal connection; per the datasheet note, unused pins of this type may be tied to either VDD or VSS. |+| 7 | VSS | power_in | Negative supply (ground) pin for the device. |+| 8 | NC | unconnected | No internal connection; per the datasheet note, unused pins of this type may be tied to either VDD or VSS. |+| 9 | E | input | Input E to the 8-input NOR/OR gate; protected by internal CMOS protection network. |+| 10 | F | input | Input F to the 8-input NOR/OR gate; protected by internal CMOS protection network. |+| 11 | G | input | Input G to the 8-input NOR/OR gate; protected by internal CMOS protection network. |+| 12 | H | input | Input H to the 8-input NOR/OR gate; protected by internal CMOS protection network. |+| 13 | J | output | NOR-gate output, J = NOR(A,B,C,D,E,F,G,H), the inverted (NOR) combination of all eight inputs. |+| 14 | VDD | power_in | Positive supply voltage pin for the device. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-14 |+| Category | Logic |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `CD4078BM96`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D, STEP)+- 3D model files: `cd4078bm96-etched.step` / `cd4078bm96-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4078bm96.step` / `cd4078bm96.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd4078b) (20 pp, sha256 `d1d07c50981c9d3a`, retrieved 2026-09-23, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-sonnet-5` (text+vision), consensus `claude-opus-4-8` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4078bm96-datasheet.pdf)
page.jsonadded+180@@ -0,0 +1,180 @@+{+ "slug": "cd4078bm96",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Logic Gates, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "cd4078bm96",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cd4078bm96.kicad_sym",+ "cd4078bm96.kicad_mod",+ "cd4078bm96.glb",+ "cd4078bm96.step",+ "cd4078bm96.lbr",+ "docs/hero.png",+ "docs/cd4078bm96-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "CD4078BM96",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-14",+ "pin_count": 14,+ "category": "Logic",+ "subcategory": "Logic Gates",+ "datasheet": "https://www.ti.com/cn/lit/gpn/cd4078b",+ "parts": {+ "symbol": "cd4078bm96.kicad_sym",+ "footprint": "cd4078bm96.kicad_mod",+ "model_3d": "cd4078bm96-etched.glb",+ "model_3d_plain": "cd4078bm96.glb",+ "model_3d_step": "cd4078bm96-etched.step",+ "model_3d_step_plain": "cd4078bm96.step",+ "lbr": "cd4078bm96.lbr"+ },+ "distributor_links": {+ "lcsc": "C84464"+ },+ "pins": [+ {+ "number": "1",+ "name": "K",+ "type": "output",+ "description": "OR-gate output, K = A+B+C+D+E+F+G+H (non-inverted OR of all eight inputs)."+ },+ {+ "number": "2",+ "name": "A",+ "type": "input",+ "description": "Input A to the 8-input NOR/OR gate; protected by internal CMOS protection network."+ },+ {+ "number": "3",+ "name": "B",+ "type": "input",+ "description": "Input B to the 8-input NOR/OR gate; protected by internal CMOS protection network."+ },+ {+ "number": "4",+ "name": "C",+ "type": "input",+ "description": "Input C to the 8-input NOR/OR gate; protected by internal CMOS protection network."+ },+ {+ "number": "5",+ "name": "D",+ "type": "input",+ "description": "Input D to the 8-input NOR/OR gate; protected by internal CMOS protection network."+ },+ {+ "number": "6",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection; per the datasheet note, unused pins of this type may be tied to either VDD or VSS."+ },+ {+ "number": "7",+ "name": "VSS",+ "type": "power_in",+ "description": "Negative supply (ground) pin for the device."+ },+ {+ "number": "8",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection; per the datasheet note, unused pins of this type may be tied to either VDD or VSS."+ },+ {+ "number": "9",+ "name": "E",+ "type": "input",+ "description": "Input E to the 8-input NOR/OR gate; protected by internal CMOS protection network."+ },+ {+ "number": "10",+ "name": "F",+ "type": "input",+ "description": "Input F to the 8-input NOR/OR gate; protected by internal CMOS protection network."+ },+ {+ "number": "11",+ "name": "G",+ "type": "input",+ "description": "Input G to the 8-input NOR/OR gate; protected by internal CMOS protection network."+ },+ {+ "number": "12",+ "name": "H",+ "type": "input",+ "description": "Input H to the 8-input NOR/OR gate; protected by internal CMOS protection network."+ },+ {+ "number": "13",+ "name": "J",+ "type": "output",+ "description": "NOR-gate output, J = NOR(A,B,C,D,E,F,G,H), the inverted (NOR) combination of all eight inputs."+ },+ {+ "number": "14",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply voltage pin for the device."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-sonnet-5",+ "primary_mode": "text+vision",+ "consensus_model": "claude-opus-4-8",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The terminal-assignment diagram used for pin numbering is labeled 'TERMINAL ASSIGNMENT' and applies ",+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 20,+ "cost_usd": 0.5623,+ "at": "2026-09-23T14:47:25"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cd4078b",+ "pages": 20,+ "sha256": "d1d07c50981c9d3a",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}