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Initial commit: component/cd4071

Ray ·93f44c813f ·2mo ago
2 files changed +109
README.mdadded+73
@@ -0,0 +1,73 @@+# CD4071B++**Texas Instruments** · Logic Gate · SOIC-14++The CD4071B contains four independent 2-input OR gates; each output is high when either input is high. It runs from 3 V to 18 V, part of the 4000B CMOS logic family.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | A | input | Gate 1 input A. CMOS logic input, VIH min 3.5 V @ VDD=5 V. Input protected by CMOS protection network. |+| 2 | B | input | Gate 1 input B. CMOS logic input paired with A to form OR gate 1 (J = A+B). |+| 3 | J | output | Gate 1 output, J = A + B. CMOS push-pull output; IOL/IOH ≈ 0.51 mA min @ VDD=5 V, VOL/VOH ≤ 0.05 V/≥ 4.95 V. |+| 4 | K | output | Gate 2 output, K = C + D. CMOS push-pull output. |+| 5 | C | input | Gate 2 input C. CMOS logic input. |+| 6 | D | input | Gate 2 input D. CMOS logic input paired with C to form OR gate 2 (K = C+D). |+| 7 | VSS | power_in | Negative supply / ground reference (0 V). All logic levels referenced to VSS. |+| 8 | E | input | Gate 3 input E. CMOS logic input. |+| 9 | F | input | Gate 3 input F. CMOS logic input paired with E to form OR gate 3 (L = E+F). |+| 10 | L | output | Gate 3 output, L = E + F. CMOS push-pull output. |+| 11 | M | output | Gate 4 output, M = G + H. CMOS push-pull output. |+| 12 | G | input | Gate 4 input G. CMOS logic input. |+| 13 | H | input | Gate 4 input H. CMOS logic input paired with G to form OR gate 4 (M = G+H). |+| 14 | VDD | power_in | Positive supply voltage. Operating range 3-18 V (absolute max −0.5 V to +20 V). Bypass to VSS with 0.1 µF ceramic capacitor near the device. |++## Key specifications++| Parameter | Value |+|---|---|+| Type | Quad OR Gate |+| Logic family | 4000B (CMOS) |+| Supply voltage | 3 V to 18 V |+| Propagation delay | 45 ns typ at 10 V |+| Operating temperature | -55 C to 125 C |++## Ordering variants++- `CD4071BE`+- `CD4071BEE4`+- `CD4071BF`+- `CD4071BF3A`+- `CD4071BM`+- `CD4071BM96`+- `CD4071BME4`+- `CD4071BMG4`+- `CD4071BMT`+- `CD4071BMTE4`+- `CD4071BMTG4`+- `CD4071BNSR`+- `CD4071BNSRE4`+- `CD4071BNSRG4`+- `CD4071BPW`+- `CD4071BPWE4`+- `CD4071BPWG4`+- `CD4071BPWR`+- `CD4071BPWRE4`+- `CD4071BPWRG4`++## CAD (KiCad official)++- Symbol: `cd4071.kicad_sym`+- Footprint: `cd4071.kicad_mod`+- 3D model: SOIC-14 body from KiCad `Package_SO/SOIC-14_3.9x8.7mm_P1.27mm`.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd4071b.pdf) (34 pp, sha256 `8611af98ab021775`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4071-datasheet.pdf)
page.jsonadded+36
@@ -0,0 +1,36 @@+{+  "slug": "cd4071",+  "version": "0.1.0",+  "type": "component",+  "description": "Quad OR Gate in the 4000B CMOS family, 3 V to 18 V.",+  "tags": [+    "logic",+    "gate",+    "4000-series",+    "cmos",+    "ti",+    "soic-14"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "cd4071.kicad_sym",+    "cd4071.kicad_mod",+    "cd4071.glb",+    "cd4071.step",+    "docs/hero.png",+    "docs/cd4071-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file