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CAD + datasheet + .step

Ray ·0b6ba10512 ·2mo ago ·parent 0dc2a4c
1 file changed +155−8
page.json+155−8
@@ -1,8 +1,11 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "cd4071",+  "title": "CD4071B Quad OR Gate",+  "brief": "Quad OR Gate in the 4000B CMOS family, 3 V to 18 V.",   "version": "0.1.0",-  "type": "component",-  "description": "Quad OR Gate in the 4000B CMOS family, 3 V to 18 V.",+  "license": "CC-BY-SA-4.0",   "tags": [     "logic",     "gate",@@ -11,6 +14,155 @@     "ti",     "soic-14"   ],+  "component": {+    "mpn": "CD4071B",+    "manufacturer": "Texas Instruments",+    "package": "SOIC-14",+    "pin_count": 14,+    "category": "Logic",+    "subcategory": "Logic Gate",+    "datasheet": "https://www.ti.com/lit/ds/symlink/cd4071b.pdf",+    "parts": {+      "symbol": "cd4071.kicad_sym",+      "footprint": "cd4071.kicad_mod",+      "model_3d": "cd4071.glb",+      "model_3d_step": "cd4071.step"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "A",+        "type": "input",+        "description": "Gate 1 input A. CMOS logic input, VIH min 3.5 V @ VDD=5 V. Input protected by CMOS protection network."+      },+      {+        "number": "2",+        "name": "B",+        "type": "input",+        "description": "Gate 1 input B. CMOS logic input paired with A to form OR gate 1 (J = A+B)."+      },+      {+        "number": "3",+        "name": "J",+        "type": "output",+        "description": "Gate 1 output, J = A + B. CMOS push-pull output; IOL/IOH \u2248 0.51 mA min @ VDD=5 V, VOL/VOH \u2264 0.05 V/\u2265 4.95 V."+      },+      {+        "number": "4",+        "name": "K",+        "type": "output",+        "description": "Gate 2 output, K = C + D. CMOS push-pull output."+      },+      {+        "number": "5",+        "name": "C",+        "type": "input",+        "description": "Gate 2 input C. CMOS logic input."+      },+      {+        "number": "6",+        "name": "D",+        "type": "input",+        "description": "Gate 2 input D. CMOS logic input paired with C to form OR gate 2 (K = C+D)."+      },+      {+        "number": "7",+        "name": "VSS",+        "type": "power_in",+        "description": "Negative supply / ground reference (0 V). All logic levels referenced to VSS."+      },+      {+        "number": "8",+        "name": "E",+        "type": "input",+        "description": "Gate 3 input E. CMOS logic input."+      },+      {+        "number": "9",+        "name": "F",+        "type": "input",+        "description": "Gate 3 input F. CMOS logic input paired with E to form OR gate 3 (L = E+F)."+      },+      {+        "number": "10",+        "name": "L",+        "type": "output",+        "description": "Gate 3 output, L = E + F. CMOS push-pull output."+      },+      {+        "number": "11",+        "name": "M",+        "type": "output",+        "description": "Gate 4 output, M = G + H. CMOS push-pull output."+      },+      {+        "number": "12",+        "name": "G",+        "type": "input",+        "description": "Gate 4 input G. CMOS logic input."+      },+      {+        "number": "13",+        "name": "H",+        "type": "input",+        "description": "Gate 4 input H. CMOS logic input paired with G to form OR gate 4 (M = G+H)."+      },+      {+        "number": "14",+        "name": "VDD",+        "type": "power_in",+        "description": "Positive supply voltage. Operating range 3-18 V (absolute max \u22120.5 V to +20 V). Bypass to VSS with 0.1 \u00b5F ceramic capacitor near the device."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://www.ti.com/lit/ds/symlink/cd4071b.pdf",+        "pages": 34,+        "sha256": "8611af98ab021775",+        "source_tier": "mfr"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 14,+        "described": 14,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Type": "Quad OR Gate",+      "Logic family": "4000B (CMOS)",+      "Supply voltage": "3 V to 18 V",+      "Propagation delay": "45 ns typ at 10 V",+      "Operating temperature": "-55 C to 125 C"+    }+  },+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "Quad OR Gate",+    "CMOS logic",+    "wide-voltage logic",+    "glue logic"+  ],+  "discovery_pitch": "The CD4071B contains four independent 2-input OR gates; each output is high when either input is high.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -27,10 +179,5 @@     "docs/cd4071-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file