component
CD4070B Quad XOR Gate
Public Made by Adomby adom
Quad 2-input exclusive-OR (XOR) gate in the 4000B CMOS family, 3 V to 18 V.
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page.json+157−8@@ -1,8 +1,11 @@ {+ "schema_version": 1,+ "type": "component", "slug": "cd4070",+ "title": "CD4070B Quad XOR Gate",+ "brief": "Quad 2-input exclusive-OR (XOR) gate in the 4000B CMOS family, 3 V to 18 V.", "version": "0.1.0",- "type": "component",- "description": "Quad 2-input exclusive-OR (XOR) gate in the 4000B CMOS family, 3 V to 18 V.",+ "license": "CC-BY-SA-4.0", "tags": [ "logic", "xor",@@ -11,6 +14,157 @@ "ti", "soic-14" ],+ "component": {+ "mpn": "CD4070B",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-14",+ "pin_count": 14,+ "category": "Logic",+ "subcategory": "Logic Gate",+ "datasheet": "https://www.ti.com/lit/ds/symlink/cd4070b.pdf",+ "parts": {+ "symbol": "cd4070.kicad_sym",+ "footprint": "cd4070.kicad_mod",+ "model_3d": "cd4070.glb",+ "model_3d_step": "cd4070.step"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "A",+ "type": "input",+ "description": "Gate 1 input A. CMOS logic input, VIH >= 3.5V at VDD=5V, 7V at VDD=10V, 11V at VDD=15V. Protected by CMOS input protection network. Paired with pin 2 (B) to produce J = A XOR B on pin 3."+ },+ {+ "number": "2",+ "name": "B",+ "type": "input",+ "description": "Gate 1 input B. CMOS logic input, VIH >= 3.5V at VDD=5V, 7V at VDD=10V, 11V at VDD=15V. Protected by CMOS input protection network. Paired with pin 1 (A) to produce J = A XOR B on pin 3."+ },+ {+ "number": "3",+ "name": "J",+ "type": "output",+ "description": "Gate 1 output, J = A XOR B (pins 1 XOR 2). Push-pull CMOS output. IOL >= 1.3mA sink, IOH >= 1.3mA source at VDD=10V (typical)."+ },+ {+ "number": "4",+ "name": "K",+ "type": "output",+ "description": "Gate 2 output, K = C XOR D (pins 5 XOR 6). Push-pull CMOS output. IOL >= 1.3mA sink, IOH >= 1.3mA source at VDD=10V (typical)."+ },+ {+ "number": "5",+ "name": "C",+ "type": "input",+ "description": "Gate 2 input C. CMOS logic input, VIH >= 3.5V at VDD=5V, 7V at VDD=10V, 11V at VDD=15V. Protected by CMOS input protection network. Paired with pin 6 (D) to produce K = C XOR D on pin 4."+ },+ {+ "number": "6",+ "name": "D",+ "type": "input",+ "description": "Gate 2 input D. CMOS logic input, VIH >= 3.5V at VDD=5V, 7V at VDD=10V, 11V at VDD=15V. Protected by CMOS input protection network. Paired with pin 5 (C) to produce K = C XOR D on pin 4."+ },+ {+ "number": "7",+ "name": "VSS",+ "type": "power_in",+ "description": "Negative supply / ground reference (0 V). All input/output voltages are referenced to VSS."+ },+ {+ "number": "8",+ "name": "E",+ "type": "input",+ "description": "Gate 3 input E. CMOS logic input, VIH >= 3.5V at VDD=5V, 7V at VDD=10V, 11V at VDD=15V. Protected by CMOS input protection network. Paired with pin 9 (F) to produce L = E XOR F on pin 10."+ },+ {+ "number": "9",+ "name": "F",+ "type": "input",+ "description": "Gate 3 input F. CMOS logic input, VIH >= 3.5V at VDD=5V, 7V at VDD=10V, 11V at VDD=15V. Protected by CMOS input protection network. Paired with pin 8 (E) to produce L = E XOR F on pin 10."+ },+ {+ "number": "10",+ "name": "L",+ "type": "output",+ "description": "Gate 3 output, L = E XOR F (pins 8 XOR 9). Push-pull CMOS output. IOL >= 1.3mA sink, IOH >= 1.3mA source at VDD=10V (typical)."+ },+ {+ "number": "11",+ "name": "M",+ "type": "output",+ "description": "Gate 4 output, M = G XOR H (pins 12 XOR 13). Push-pull CMOS output. IOL >= 1.3mA sink, IOH >= 1.3mA source at VDD=10V (typical)."+ },+ {+ "number": "12",+ "name": "G",+ "type": "input",+ "description": "Gate 4 input G. CMOS logic input, VIH >= 3.5V at VDD=5V, 7V at VDD=10V, 11V at VDD=15V. Protected by CMOS input protection network. Paired with pin 13 (H) to produce M = G XOR H on pin 11."+ },+ {+ "number": "13",+ "name": "H",+ "type": "input",+ "description": "Gate 4 input H. CMOS logic input, VIH >= 3.5V at VDD=5V, 7V at VDD=10V, 11V at VDD=15V. Protected by CMOS input protection network. Paired with pin 12 (G) to produce M = G XOR H on pin 11."+ },+ {+ "number": "14",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply. Operating range 3 V to 18 V (absolute maximum 20 V). Bypass with a 100 nF ceramic capacitor to VSS close to the pin."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/cd4070b.pdf",+ "pages": 34,+ "sha256": "0a62a1cbf7f15360",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Type": "Quad 2-input XOR gate",+ "Logic family": "4000B (CMOS)",+ "Gates": "4 XOR",+ "Supply voltage": "3 V to 18 V",+ "Propagation delay": "65 ns typ at 10 V",+ "Operating temperature": "-55 C to 125 C"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "XOR gate",+ "exclusive OR",+ "parity",+ "controlled inverter",+ "comparator logic"+ ],+ "discovery_pitch": "Four XOR gates for parity, controlled inversion, and single-bit comparison, across a wide 3 V to 18 V supply.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -27,10 +181,5 @@ "docs/cd4070-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }