← Commit history

CAD + datasheet + .step

Ray ·f71128d023 ·2mo ago ·parent ee95118
1 file changed +157−8
page.json+157−8
@@ -1,8 +1,11 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "cd4069",+  "title": "CD4069UB Hex Inverter",+  "brief": "Hex (six) inverter in the 4000B CMOS family, unbuffered, 3 V to 18 V.",   "version": "0.1.0",-  "type": "component",-  "description": "Hex (six) inverter in the 4000B CMOS family, unbuffered, 3 V to 18 V.",+  "license": "CC-BY-SA-4.0",   "tags": [     "logic",     "inverter",@@ -11,6 +14,157 @@     "ti",     "soic-14"   ],+  "component": {+    "mpn": "CD4069UB",+    "manufacturer": "Texas Instruments",+    "package": "SOIC-14",+    "pin_count": 14,+    "category": "Logic",+    "subcategory": "Logic Gate",+    "datasheet": "https://www.ti.com/lit/ds/symlink/cd4069ub.pdf",+    "parts": {+      "symbol": "cd4069.kicad_sym",+      "footprint": "cd4069.kicad_mod",+      "model_3d": "cd4069.glb",+      "model_3d_step": "cd4069.step"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "A",+        "type": "input",+        "description": "Inverter A input (channel 1). CMOS logic input, VIL \u2264 1 V @ VDD=5 V, VIH \u2265 4 V @ VDD=5 V. Input current typically \u00b110 pA @ 25 \u00b0C, \u00b11 \u00b5A max over full temperature range. Input capacitance 10 pF typ, 15 pF max."+      },+      {+        "number": "2",+        "name": "G",+        "type": "output",+        "description": "Inverter A output (G = NOT A). CMOS push-pull output. VOH \u2265 VDD \u2212 0.05 V, VOL \u2264 0.05 V. Sinks ~0.51 mA typ (VO=0.4 V, VDD=5 V); sources ~-0.51 mA typ (VO=4.6 V, VDD=5 V). Dissipation \u2264100 mW per output transistor."+      },+      {+        "number": "3",+        "name": "B",+        "type": "input",+        "description": "Inverter B input (channel 2). CMOS logic input; same electrical thresholds as pin 1."+      },+      {+        "number": "4",+        "name": "H",+        "type": "output",+        "description": "Inverter B output (H = NOT B). CMOS push-pull output; same drive characteristics as pin 2."+      },+      {+        "number": "5",+        "name": "C",+        "type": "input",+        "description": "Inverter C input (channel 3). CMOS logic input; same electrical thresholds as pin 1."+      },+      {+        "number": "6",+        "name": "I",+        "type": "output",+        "description": "Inverter C output (I = NOT C). CMOS push-pull output; same drive characteristics as pin 2."+      },+      {+        "number": "7",+        "name": "VSS",+        "type": "power_in",+        "description": "Negative supply / ground reference. All voltages referenced to VSS. Typically tied to 0 V."+      },+      {+        "number": "8",+        "name": "J",+        "type": "output",+        "description": "Inverter D output (J = NOT D). CMOS push-pull output; same drive characteristics as pin 2."+      },+      {+        "number": "9",+        "name": "D",+        "type": "input",+        "description": "Inverter D input (channel 4). CMOS logic input; same electrical thresholds as pin 1."+      },+      {+        "number": "10",+        "name": "K",+        "type": "output",+        "description": "Inverter E output (K = NOT E). CMOS push-pull output; same drive characteristics as pin 2."+      },+      {+        "number": "11",+        "name": "E",+        "type": "input",+        "description": "Inverter E input (channel 5). CMOS logic input; same electrical thresholds as pin 1."+      },+      {+        "number": "12",+        "name": "L",+        "type": "output",+        "description": "Inverter F output (L = NOT F). CMOS push-pull output; same drive characteristics as pin 2."+      },+      {+        "number": "13",+        "name": "F",+        "type": "input",+        "description": "Inverter F input (channel 6). CMOS logic input; same electrical thresholds as pin 1."+      },+      {+        "number": "14",+        "name": "VDD",+        "type": "power_in",+        "description": "Positive supply. Recommended operating range 3 V to 18 V (absolute max 20 V). Bypass with a 100 nF ceramic close to the pin."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://www.ti.com/lit/ds/symlink/cd4069ub.pdf",+        "pages": 34,+        "sha256": "bb3ad731a488a86f",+        "source_tier": "mfr"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 14,+        "described": 14,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Type": "Hex inverter (unbuffered)",+      "Logic family": "4000B (CMOS)",+      "Gates": "6 inverters",+      "Supply voltage": "3 V to 18 V",+      "Propagation delay": "30 ns typ at 10 V",+      "Operating temperature": "-55 C to 125 C"+    }+  },+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "hex inverter",+    "six inverters",+    "NOT gate",+    "CMOS oscillator",+    "logic inversion"+  ],+  "discovery_pitch": "Six inverters in one package, useful for logic inversion and as unbuffered gain stages in RC and crystal oscillators.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -27,10 +181,5 @@     "docs/cd4069-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file