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cd4060dm: factory component page (tier=lcsc)

Ray ·a3addf56ab · ·parent 8761591
1 file changed +182−8
page.json+182−8
@@ -1,13 +1,192 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "cd4060dm",+  "title": "CD4060DM",+  "brief": "HGSEMI Counters / Dividers, SOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",-  "type": "component",-  "description": "HGSEMI Counters / Dividers, SOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "logic",     "cd4060dm"   ],+  "component": {+    "mpn": "CD4060DM",+    "manufacturer": "HGSEMI",+    "package": "SOP-16",+    "pin_count": 16,+    "category": "Logic",+    "subcategory": "Counters / Dividers",+    "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2404031725_HGSEMI-CD4060DM-TR_C7432175.pdf",+    "parts": {+      "symbol": "cd4060dm.kicad_sym",+      "footprint": "cd4060dm.kicad_mod",+      "model_3d": "cd4060dm.glb",+      "model_3d_step": "cd4060dm.step",+      "lbr": "cd4060dm.lbr"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "Q12",+        "type": "output",+        "description": "Counter output stage 12. CMOS push-pull output driven by the 14-stage binary ripple counter; toggles at fCLK/2^12."+      },+      {+        "number": "2",+        "name": "Q13",+        "type": "output",+        "description": "Counter output stage 13. CMOS push-pull output; toggles at fCLK/2^13."+      },+      {+        "number": "3",+        "name": "Q14",+        "type": "output",+        "description": "Counter output stage 14 (final stage). CMOS push-pull output; toggles at fCLK/2^14."+      },+      {+        "number": "4",+        "name": "Q6",+        "type": "output",+        "description": "Counter output stage 6. CMOS push-pull output; toggles at fCLK/2^6."+      },+      {+        "number": "5",+        "name": "Q5",+        "type": "output",+        "description": "Counter output stage 5. CMOS push-pull output; toggles at fCLK/2^5."+      },+      {+        "number": "6",+        "name": "Q7",+        "type": "output",+        "description": "Counter output stage 7. CMOS push-pull output; toggles at fCLK/2^7."+      },+      {+        "number": "7",+        "name": "Q4",+        "type": "output",+        "description": "Counter output stage 4. CMOS push-pull output; toggles at fCLK/2^4."+      },+      {+        "number": "8",+        "name": "VSS",+        "type": "power_in",+        "description": "Negative supply / ground reference (0 V). Recommended supply range VDD-VSS = 3 V to 15 V."+      },+      {+        "number": "9",+        "name": "\u03a60",+        "type": "output",+        "description": "Oscillator buffered clock output (Phi0). Connects to the external RC or crystal network together with pins 10 and 11 to form the on-chip oscillator."+      },+      {+        "number": "10",+        "name": "\u03a60_bar",+        "type": "output",+        "description": "Inverted oscillator output (Phi0 with overbar). Used with pin 9 (\u03a60) and pin 11 (\u03a6I) to bias the external RC or crystal oscillator network."+      },+      {+        "number": "11",+        "name": "\u03a6I",+        "type": "input",+        "description": "Oscillator/clock input (PhiI). Schmitt-trigger input; tied to the external RC or crystal network, or driven directly by an external clock source."+      },+      {+        "number": "12",+        "name": "RESET",+        "type": "input",+        "description": "Active-high asynchronous master reset. When high, all counter stages are cleared to 0 and the internal oscillator is disabled. Should be tied to VSS for normal counting operation."+      },+      {+        "number": "13",+        "name": "Q9",+        "type": "output",+        "description": "Counter output stage 9. CMOS push-pull output; toggles at fCLK/2^9."+      },+      {+        "number": "14",+        "name": "Q8",+        "type": "output",+        "description": "Counter output stage 8. CMOS push-pull output; toggles at fCLK/2^8."+      },+      {+        "number": "15",+        "name": "Q10",+        "type": "output",+        "description": "Counter output stage 10. CMOS push-pull output; toggles at fCLK/2^10."+      },+      {+        "number": "16",+        "name": "VDD",+        "type": "power_in",+        "description": "Positive supply pin. Recommended VDD-VSS operating range 3 V to 15 V; absolute max 18 V."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2404031725_HGSEMI-CD4060DM-TR_C7432175.pdf",+        "pages": 9,+        "sha256": "429b5643241501b2",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 16,+        "described": 16,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Manufacturer": "HGSEMI",+      "Package": "SOP-16",+      "Category": "Logic",+      "Pins": "16"+    }+  },+  "variants": [+    {+      "mpn": "CD4060DM/TR",+      "kind": "packaging"+    },+    {+      "mpn": "CD4060DMDE",+      "kind": "packaging"+    },+    {+      "mpn": "CD4060DMDN",+      "kind": "packaging"+    },+    {+      "mpn": "CD4060DMT/TR",+      "kind": "packaging"+    }+  ],+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "cd4060dm"+  ],+  "discovery_pitch": "CD4060DM (HGSEMI) component page with datasheet-verified CAD.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -25,10 +204,5 @@     "docs/cd4060dm-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file