component
CD4060BM
Public Made by Adomby adom
lingxingic Counters, Dividers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# CD4060BM++**lingxingic** · Counters, Dividers · SOP-16++CD4060BM from lingxingic, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | Q11 | output | Counter output; logic level indicates stage 11 of 14-stage binary counter. |+| 2 | Q12 | output | Counter output; logic level indicates stage 12 of 14-stage binary counter. |+| 3 | Q13 | output | Counter output; logic level indicates stage 13 of 14-stage binary counter. |+| 4 | Q5 | output | Counter output; logic level indicates stage 5 of 14-stage binary counter. |+| 5 | Q4 | output | Counter output; logic level indicates stage 4 of 14-stage binary counter. |+| 6 | Q6 | output | Counter output; logic level indicates stage 6 of 14-stage binary counter. |+| 7 | Q3 | output | Counter output; logic level indicates stage 3 of 14-stage binary counter. |+| 8 | VSS | power_in | Ground reference at 0V; common ground return for all circuits. |+| 9 | CEXT | passive | External capacitor connection for RC oscillator circuit; connects timing capacitor. |+| 10 | REXT | passive | Oscillator pin for external resistor connection; sets oscillation frequency in RC mode. |+| 11 | RS | input | Clock input or oscillator pin; counter advances on negative-going transition; input pulse frequency 3.5-12 MHz depending on VDD. |+| 12 | MR | input | Master reset input; HIGH level asynchronously resets counter outputs Q3 to Q9 and Q11 to Q13 to LOW. |+| 13 | Q8 | output | Counter output; logic level indicates stage 8 of 14-stage binary counter. |+| 14 | Q7 | output | Counter output; logic level indicates stage 7 of 14-stage binary counter. |+| 15 | Q9 | output | Counter output; logic level indicates stage 9 of 14-stage binary counter. |+| 16 | VDD | power_in | Supply voltage input; operating range 3 V to 15 V referenced to VSS. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | lingxingic |+| Package | SOP-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CD4060BM`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOP-16 (KiCad packages3D, STEP)+- 3D model files: `cd4060bm-etched.step` / `cd4060bm-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4060bm.step` / `cd4060bm.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [lingxingic datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603372372477571072) (16 pp, sha256 `912b5a56dff08e32`, retrieved 2026-09-21, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4060bm-datasheet.pdf)
page.jsonadded+189@@ -0,0 +1,189 @@+{+ "slug": "cd4060bm",+ "version": "0.1.0",+ "type": "component",+ "description": "lingxingic Counters, Dividers, SOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "cd4060bm",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cd4060bm.kicad_sym",+ "cd4060bm.kicad_mod",+ "cd4060bm.glb",+ "cd4060bm.step",+ "cd4060bm.lbr",+ "docs/hero.png",+ "docs/cd4060bm-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "CD4060BM",+ "manufacturer": "lingxingic",+ "package": "SOP-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Counters, Dividers",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603372372477571072",+ "parts": {+ "symbol": "cd4060bm.kicad_sym",+ "footprint": "cd4060bm.kicad_mod",+ "model_3d": "cd4060bm-etched.glb",+ "model_3d_plain": "cd4060bm.glb",+ "model_3d_step": "cd4060bm-etched.step",+ "model_3d_step_plain": "cd4060bm.step",+ "lbr": "cd4060bm.lbr"+ },+ "distributor_links": {+ "lcsc": "C24833623"+ },+ "pins": [+ {+ "number": "1",+ "name": "Q11",+ "type": "output",+ "description": "Counter output; logic level indicates stage 11 of 14-stage binary counter."+ },+ {+ "number": "2",+ "name": "Q12",+ "type": "output",+ "description": "Counter output; logic level indicates stage 12 of 14-stage binary counter."+ },+ {+ "number": "3",+ "name": "Q13",+ "type": "output",+ "description": "Counter output; logic level indicates stage 13 of 14-stage binary counter."+ },+ {+ "number": "4",+ "name": "Q5",+ "type": "output",+ "description": "Counter output; logic level indicates stage 5 of 14-stage binary counter."+ },+ {+ "number": "5",+ "name": "Q4",+ "type": "output",+ "description": "Counter output; logic level indicates stage 4 of 14-stage binary counter."+ },+ {+ "number": "6",+ "name": "Q6",+ "type": "output",+ "description": "Counter output; logic level indicates stage 6 of 14-stage binary counter."+ },+ {+ "number": "7",+ "name": "Q3",+ "type": "output",+ "description": "Counter output; logic level indicates stage 3 of 14-stage binary counter."+ },+ {+ "number": "8",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference at 0V; common ground return for all circuits."+ },+ {+ "number": "9",+ "name": "CEXT",+ "type": "passive",+ "description": "External capacitor connection for RC oscillator circuit; connects timing capacitor."+ },+ {+ "number": "10",+ "name": "REXT",+ "type": "passive",+ "description": "Oscillator pin for external resistor connection; sets oscillation frequency in RC mode."+ },+ {+ "number": "11",+ "name": "RS",+ "type": "input",+ "description": "Clock input or oscillator pin; counter advances on negative-going transition; input pulse frequency 3.5-12 MHz depending on VDD."+ },+ {+ "number": "12",+ "name": "MR",+ "type": "input",+ "description": "Master reset input; HIGH level asynchronously resets counter outputs Q3 to Q9 and Q11 to Q13 to LOW."+ },+ {+ "number": "13",+ "name": "Q8",+ "type": "output",+ "description": "Counter output; logic level indicates stage 8 of 14-stage binary counter."+ },+ {+ "number": "14",+ "name": "Q7",+ "type": "output",+ "description": "Counter output; logic level indicates stage 7 of 14-stage binary counter."+ },+ {+ "number": "15",+ "name": "Q9",+ "type": "output",+ "description": "Counter output; logic level indicates stage 9 of 14-stage binary counter."+ },+ {+ "number": "16",+ "name": "VDD",+ "type": "power_in",+ "description": "Supply voltage input; operating range 3 V to 15 V referenced to VSS."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 16,+ "cost_usd": 0.1624,+ "at": "2026-09-21T16:19:01"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603372372477571072",+ "pages": 16,+ "sha256": "912b5a56dff08e32",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}