component
CD4060BDTR
Public Made by Adomby adom
XBLW Counters / Dividers, SOP-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
page.json+164−8@@ -1,13 +1,174 @@ {+ "schema_version": 1,+ "type": "component", "slug": "cd4060bdtr",+ "title": "CD4060BDTR",+ "brief": "XBLW CD4060BDTR XBLW Counters / Dividers, SOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "XBLW CD4060BDTR XBLW Counters / Dividers, SOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic", "cd4060bdtr" ],+ "component": {+ "mpn": "CD4060BDTR",+ "manufacturer": "XBLW CD4060BDTR XBLW",+ "package": "SOP-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Counters / Dividers",+ "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2310191804_XBLW-CD4060BDTR-XBLW_C18723493.pdf",+ "parts": {+ "symbol": "cd4060bdtr.kicad_sym",+ "footprint": "cd4060bdtr.kicad_mod",+ "model_3d": "cd4060bdtr.glb",+ "model_3d_step": "cd4060bdtr.step",+ "lbr": "cd4060bdtr.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "Q11",+ "type": "output",+ "description": "Buffered output of counter stage 12 (divide-by-4096). CMOS output, VDD swing."+ },+ {+ "number": "2",+ "name": "Q12",+ "type": "output",+ "description": "Buffered output of counter stage 13 (divide-by-8192). CMOS output, VDD swing."+ },+ {+ "number": "3",+ "name": "Q13",+ "type": "output",+ "description": "Buffered output of counter stage 14 (divide-by-16384). CMOS output, VDD swing."+ },+ {+ "number": "4",+ "name": "Q9",+ "type": "output",+ "description": "Buffered output of counter stage 10 (divide-by-1024). CMOS output, VDD swing."+ },+ {+ "number": "5",+ "name": "Q8",+ "type": "output",+ "description": "Buffered output of counter stage 9 (divide-by-512). CMOS output, VDD swing."+ },+ {+ "number": "6",+ "name": "Q7",+ "type": "output",+ "description": "Buffered output of counter stage 8 (divide-by-256). CMOS output, VDD swing."+ },+ {+ "number": "7",+ "name": "Q5",+ "type": "output",+ "description": "Buffered output of counter stage 6 (divide-by-64). CMOS output, VDD swing."+ },+ {+ "number": "8",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference (0 V)."+ },+ {+ "number": "9",+ "name": "RS",+ "type": "output",+ "description": "Oscillator RC network connection (reset/feedback node between external RS and CTC of the RC oscillator)."+ },+ {+ "number": "10",+ "name": "RTC",+ "type": "input",+ "description": "Oscillator RC timing input node (RTC / external clock input when oscillator is not used)."+ },+ {+ "number": "11",+ "name": "CTC",+ "type": "passive",+ "description": "Oscillator timing capacitor connection (CTC)."+ },+ {+ "number": "12",+ "name": "RESET",+ "type": "input",+ "description": "Master reset input. A logic HIGH clears all counter stages and disables the oscillator; must be held LOW for normal counting."+ },+ {+ "number": "13",+ "name": "Q6",+ "type": "output",+ "description": "Buffered output of counter stage 7 (divide-by-128). CMOS output, VDD swing."+ },+ {+ "number": "14",+ "name": "Q4",+ "type": "output",+ "description": "Buffered output of counter stage 5 (divide-by-32). CMOS output, VDD swing."+ },+ {+ "number": "15",+ "name": "Q3",+ "type": "output",+ "description": "Buffered output of counter stage 4 (divide-by-16). CMOS output, VDD swing."+ },+ {+ "number": "16",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply voltage. Operating range 3 V to 18 V."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2310191804_XBLW-CD4060BDTR-XBLW_C18723493.pdf",+ "pages": 15,+ "sha256": "fc074a4a0bd1cffe",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "XBLW CD4060BDTR XBLW",+ "Package": "SOP-16",+ "Category": "Logic",+ "Pins": "16"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "cd4060bdtr"+ ],+ "discovery_pitch": "CD4060BDTR (XBLW CD4060BDTR XBLW) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +186,5 @@ "docs/cd4060bdtr-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }