← Commit history

orderable attributes: rebuild .lbr with adom-lbr 2.18.0 so MPN, MANUFACTURER and the distributor part numbers reach <technology> (DIGIKEY_PN 296-14273-2-ND, LCSC_PN C6522). The published library carried no attributes at all, so a BOM had nothing to buy from. Distributor PNs matched on exact MPN AND corroborating manufacturer.

Ray ·8c435cbd85 ·2mo ago ·parent 94d1678
2 files changed +27−5
cd4052bpwr.lbr+21−2
@@ -70,11 +70,23 @@   <smd name="14" x="2.8625" y="0.9750" dx="1.4750" dy="0.4000" layer="1"/>   <smd name="15" x="2.8625" y="1.6250" dx="1.4750" dy="0.4000" layer="1"/>   <smd name="16" x="2.8625" y="2.2750" dx="1.4750" dy="0.4000" layer="1"/>+  <polygon width="0.1200" layer="21">+    <vertex x="-3.8600" y="2.2800"/>+    <vertex x="-4.1900" y="2.0400"/>+    <vertex x="-4.1900" y="2.5200"/>+  </polygon>+  <polygon width="0.1000" layer="51">+    <vertex x="-1.2000" y="2.5000"/>+    <vertex x="2.2000" y="2.5000"/>+    <vertex x="2.2000" y="-2.5000"/>+    <vertex x="-2.2000" y="-2.5000"/>+    <vertex x="-2.2000" y="1.5000"/>+  </polygon>   <wire x1="-2.3100" y1="2.7350" x2="2.3100" y2="2.7350" width="0.1200" layer="21"/>   <wire x1="2.3100" y1="-2.7350" x2="-2.3100" y2="-2.7350" width="0.1200" layer="21"/>   <text x="0" y="3.613" size="1.27" layer="25" align="bottom-center">&gt;NAME</text>   <text x="0" y="-3.613" size="1.27" layer="27" align="top-center">&gt;VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-3.8600" y="2.2800"/><vertex x="-4.1900" y="2.0400"/><vertex x="-4.1900" y="2.5200"/></polygon></package>+</package> </packages> <symbols> <symbol name="CD4052BPWR">@@ -128,7 +140,14 @@         <connect gate="G$1" pin="A" pad="10"/>         <connect gate="G$1" pin="B" pad="9"/>       </connects>-      <technologies><technology name=""/></technologies>+      <technologies>+        <technology name="">+          <attribute name="MPN" value="CD4052BPWR" constant="no"/>+          <attribute name="MANUFACTURER" value="Texas Instruments" constant="no"/>+          <attribute name="DIGIKEY_PN" value="296-14273-2-ND" constant="no"/>+          <attribute name="LCSC_PN" value="C6522" constant="no"/>+        </technology>+      </technologies>     </device>   </devices> </deviceset>
page.json+6−3
@@ -26,7 +26,10 @@       "model_3d_step": "cd4052bpwr.step",       "lbr": "cd4052bpwr.lbr"     },-    "distributor_links": {},+    "distributor_links": {+      "digikey": "296-14273-2-ND",+      "lcsc": "C6522"+    },     "pins": [       {         "number": "1",@@ -68,7 +71,7 @@         "number": "7",         "name": "VEE",         "type": "power_in",-        "description": "Negative analog supply input. Sets the lower limit of the analog signal range; must satisfy VEE ≤ VSS ≤ VDD, with (VDD - VEE) ≤ 20 V."+        "description": "Negative analog supply input. Sets the lower limit of the analog signal range; must satisfy VEE \u2264 VSS \u2264 VDD, with (VDD - VEE) \u2264 20 V."       },       {         "number": "8",@@ -122,7 +125,7 @@         "number": "16",         "name": "VDD",         "type": "power_in",-        "description": "Positive supply input. 3 V to 20 V single-supply (performance degrades below 3 V); sets the upper analog and logic-high rail. (VDD - VEE) ≤ 20 V absolute max."+        "description": "Positive supply input. 3 V to 20 V single-supply (performance degrades below 3 V); sets the upper analog and logic-high rail. (VDD - VEE) \u2264 20 V absolute max."       }     ],     "provenance": {