cd4046bm

@@ -0,0 +1,58 @@+# CD4046BM++**HGSEMI** · Clock Generators / Frequency Synthesizers / PLL · SOP-16++CD4046BM from HGSEMI, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | PHASE_PULSES | output | Phase pulses output from Phase Comparator II. Provides a lock-in indication signal (high when PLL is not locked, in the tri-state region of comparator II). CMOS output referenced to VDD/VSS. |+| 2 | PHASE_COMP_I_OUT | output | Phase Comparator I output (exclusive-OR gate). Provides a digital error signal that maintains a 90° phase shift between SIGNAL_IN and COMPARATOR_IN at the VCO center frequency. CMOS output driven rail-to-rail. |+| 3 | COMPARATOR_IN | input | Common comparator input for Phase Comparator I and II. Typically driven by the VCO output (directly or via an external divide-by-N). High-impedance CMOS input (~10^6 MΩ typ.). |+| 4 | VCO_OUT | output | Voltage-controlled oscillator output. Square-wave (~50% duty cycle) whose frequency is set by VCOIN, C1 (across pins 6-7), R1 (pin 11) and R2 (pin 12). Typical transition time 45-90 ns depending on VDD. |+| 5 | INHIBIT | input | Active-high inhibit input. When high, disables the VCO and source follower to minimize standby power consumption; when low (tied to VSS), VCO and source follower are enabled. |+| 6 | C1A | passive | VCO timing capacitor terminal A. Connect external timing capacitor C1 (≥ 50 pF) between C1A (pin 6) and C1B (pin 7) to set the VCO frequency together with R1 and R2. |+| 7 | C1B | passive | VCO timing capacitor terminal B. Return side of the external timing capacitor C1 (≥ 50 pF) that sets the VCO frequency in combination with R1 and R2. |+| 8 | VSS | power_in | Negative supply / ground reference (0 V). All input and output voltages are referenced to VSS. Total supply (VDD - VSS) must be within 3.0 V to 18 V (abs. max), 3 V to 15 V recommended. |+| 9 | VCO_IN | input | VCO control-voltage input (demodulator/loop-filter input). Very high input impedance (~10^6 MΩ typ.). Driven by the loop filter fed from a phase comparator output; the voltage on this pin sets the VCO frequency between fMIN and fMAX. |+| 10 | DEMODULATOR_OUT | output | Source-follower output of the VCOIN voltage. Provides a buffered replica of the VCO control voltage for FM-demodulation output. Must be loaded with an external resistor RS ≥ 10 kΩ to VSS; offset from VCOIN is typ. 1.5 V. |+| 11 | R1 | passive | External VCO timing resistor R1 terminal (connect R1 between this pin and VSS). Sets the VCO center frequency; R1 ≥ 10 kΩ recommended. |+| 12 | R2 | passive | External VCO offset resistor R2 terminal (connect R2 between this pin and VSS, or leave open for no offset). Sets the VCO frequency offset (fMIN); R2 ≥ 10 kΩ when used. |+| 13 | PHASE_COMP_II_OUT | tri_state | Phase Comparator II output. Edge-controlled digital memory network providing a three-state (high / low / high-Z) error signal that drives the loop filter and maintains 0° phase shift between signal and comparator inputs when locked. |+| 14 | SIGNAL_IN | input | Signal input to both phase comparators. Can be DC-coupled for large-swing signals or AC-coupled (via CSERIES) to the internal self-biasing amplifier for small signals (typ. sensitivity 200 mV at VDD = 5 V, 700 mV at VDD = 15 V with 1000 pF series coupling). |+| 15 | ZENER | passive | Internal zener diode cathode, used for optional supply regulation. VZ = 7.0 V typ. (6.3-7.7 V) at IZ = 50 µA, dynamic resistance RZ ≈ 100 Ω at IZ = 1 mA. Leave open if not used. |+| 16 | VDD | power_in | Positive supply voltage. 3.0 V to 18 V (abs. max), 3 V to 15 V recommended. Bypass to VSS with a local ceramic capacitor. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | HGSEMI |+| Package | SOP-16 |+| Category | RTC |+| Pins | 16 |++## Ordering variants++- `CD4046BMBE`+- `CD4046BMBN`+- `CD4046BM/TR`+- `CD4046BMT/TR`++## CAD (KiCad official)++- Symbol: `CD4046BM`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOP-16 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [HGSEMI datasheet](docs/cd4046bm-datasheet.pdf) (None pp, sha256 `74fb8fc5a4f17a6f`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4046bm-datasheet.pdf)

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