CD4029B Up/Down Counter

@@ -0,0 +1,64 @@+# CD4029B++**Texas Instruments** · Counter · SOIC-16++The CD4029B is a presettable up/down counter that can count in binary or BCD, selected by a mode input. A direction input sets counting up or down, parallel jam inputs preset the value, and carry in/out allow cascading. It runs from 3 V to 18 V.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | PRESET_ENABLE | input | Asynchronous preset enable. When HIGH, the counter is loaded (jammed) with the state present on J1-J4 independently of the clock. When LOW, the counter is free to advance on the clock. |+| 2 | Q4 | output | Buffered counter output bit 4 (MSB). Full-rail CMOS output; IOH/IOL specified up to several mA depending on VDD (see static electrical characteristics). |+| 3 | JAM4 | input | Parallel jam (preset) data input for bit 4. Loaded into the counter when PRESET ENABLE is HIGH. |+| 4 | JAM1 | input | Parallel jam (preset) data input for bit 1 (LSB). Loaded into the counter when PRESET ENABLE is HIGH. |+| 5 | CARRY_IN | input | Active-LOW carry input, also functions as the clock enable. Counter advancement (on the positive clock transition) is inhibited when CARRY IN is HIGH; permitted when LOW. |+| 6 | Q1 | output | Buffered counter output bit 1 (LSB). Full-rail CMOS output. |+| 7 | CARRY_OUT | output | Active-LOW carry output. Normally HIGH; goes LOW when the counter reaches its maximum count in UP mode or the minimum count in DOWN mode while CARRY IN is LOW. Used to ripple-cascade to the next stage's CARRY IN. |+| 8 | VSS | power_in | Negative supply / ground reference (0 V). Tie to system GND. |+| 9 | BINARY/DECADE | input | Counter mode select. HIGH selects binary (mod-16) counting; LOW selects BCD decade (mod-10) counting. |+| 10 | UP/DOWN | input | Direction control. HIGH counts up; LOW counts down. |+| 11 | Q2 | output | Buffered counter output bit 2. Full-rail CMOS output. |+| 12 | JAM2 | input | Parallel jam (preset) data input for bit 2. Loaded into the counter when PRESET ENABLE is HIGH. |+| 13 | JAM3 | input | Parallel jam (preset) data input for bit 3. Loaded into the counter when PRESET ENABLE is HIGH. |+| 14 | Q3 | output | Buffered counter output bit 3. Full-rail CMOS output. |+| 15 | CLOCK | input | Clock input. The counter advances on the positive transition of CLOCK when CARRY IN is LOW and PRESET ENABLE is LOW. fCL up to 8 MHz typ. at VDD = 10 V. |+| 16 | VDD | power_in | Positive supply. Operating range 3 V to 18 V (absolute max -0.5 V to +20 V referenced to VSS). |++## Key specifications++| Parameter | Value |+|---|---|+| Type | Presettable binary/BCD up/down counter |+| Logic family | 4000B (CMOS) |+| Modes | Binary or BCD, up or down |+| Features | Parallel preset, carry in/out, cascadable |+| Supply voltage | 3 V to 18 V |+| Operating temperature | -55 C to 125 C |++## Ordering variants++- `CD4029BF3A`+- `CD4029BE`+- `CD4029BM`+- `CD4029BM96`+- `CD4029BMT`+- `CD4029BNSR`+- `CD4029BPW`+- `CD4029BPWR`++## CAD (KiCad official)++- Symbol: `cd4029.kicad_sym`+- Footprint: `cd4029.kicad_mod`+- 3D model: SOIC-16 body from KiCad `Package_SO/SOIC-16_3.9x9.9mm_P1.27mm`.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd4029b.pdf) (21 pp, sha256 `01f8e26c0271edc8`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4029-datasheet.pdf)

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