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CD4021BPWR
Public Made by Adomby adom
Texas Instruments Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# CD4021BPWR++**Texas Instruments** · Shift Registers · TSSOP-16++CD4021BPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | PI-8 | input | Parallel (jam) data input to register stage 8; asynchronous parallel entry when PARALLEL/SERIAL CONTROL is high (CD4021B). |+| 2 | Q6 | output | Buffered Q output tapped from internal register stage 6. |+| 3 | Q8 | output | Buffered Q output from the final register stage 8 (main serial data output). |+| 4 | PI-4 | input | Parallel (jam) data input to register stage 4; asynchronous parallel entry when PARALLEL/SERIAL CONTROL is high. |+| 5 | PI-3 | input | Parallel (jam) data input to register stage 3; asynchronous parallel entry when PARALLEL/SERIAL CONTROL is high. |+| 6 | PI-2 | input | Parallel (jam) data input to register stage 2; asynchronous parallel entry when PARALLEL/SERIAL CONTROL is high. |+| 7 | PI-1 | input | Parallel (jam) data input to register stage 1; asynchronous parallel entry when PARALLEL/SERIAL CONTROL is high. |+| 8 | VSS | power_in | Negative supply / ground return; supply-voltage range VDD to VSS is 3 V to 18 V over the full package-temperature range. |+| 9 | PARALLEL/SERIAL CONTROL | input | Mode control input: when high, data is asynchronously jammed into the 8-stage register via the parallel inputs; when low, data is shifted in serially, synchronous with the clock's positive transition. |+| 10 | CLOCK | input | Clock input; register shifts on the positive transition, with maximum clock frequency 3 MHz at VDD=5V, 6 MHz at 10V, and 8.5 MHz at 15V per the recommended operating conditions. |+| 11 | SERIAL IN | input | Single serial data input; data is shifted into the 8-stage register synchronously with the positive clock transition when PARALLEL/SERIAL CONTROL is low. |+| 12 | Q7 | output | Buffered Q output tapped from internal register stage 7. |+| 13 | PI-5 | input | Parallel (jam) data input to register stage 5; asynchronous parallel entry when PARALLEL/SERIAL CONTROL is high. |+| 14 | PI-6 | input | Parallel (jam) data input to register stage 6; asynchronous parallel entry when PARALLEL/SERIAL CONTROL is high. |+| 15 | PI-7 | input | Parallel (jam) data input to register stage 7; asynchronous parallel entry when PARALLEL/SERIAL CONTROL is high. |+| 16 | VDD | power_in | Positive supply pin; supply-voltage range VDD to VSS is 3 V to 18 V over the full package-temperature range. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CD4021BPWR`+- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`+- 3D model: TSSOP-16 (KiCad packages3D, STEP)+- 3D model files: `cd4021bpwr-etched.step` / `cd4021bpwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4021bpwr.step` / `cd4021bpwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd4021b.pdf) (29 pp, sha256 `89a926918808a607`, retrieved 2026-09-23, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-sonnet-5` (vision), consensus `claude-opus-4-8` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4021bpwr-datasheet.pdf)
page.jsonadded+191@@ -0,0 +1,191 @@+{+ "slug": "cd4021bpwr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Shift Registers, TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "cd4021bpwr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cd4021bpwr.kicad_sym",+ "cd4021bpwr.kicad_mod",+ "cd4021bpwr.glb",+ "cd4021bpwr.step",+ "cd4021bpwr.lbr",+ "docs/hero.png",+ "docs/cd4021bpwr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "CD4021BPWR",+ "manufacturer": "Texas Instruments",+ "package": "TSSOP-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Shift Registers",+ "datasheet": "https://www.ti.com/lit/ds/symlink/cd4021b.pdf",+ "parts": {+ "symbol": "cd4021bpwr.kicad_sym",+ "footprint": "cd4021bpwr.kicad_mod",+ "model_3d": "cd4021bpwr-etched.glb",+ "model_3d_plain": "cd4021bpwr.glb",+ "model_3d_step": "cd4021bpwr-etched.step",+ "model_3d_step_plain": "cd4021bpwr.step",+ "lbr": "cd4021bpwr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2877061"+ },+ "pins": [+ {+ "number": "1",+ "name": "PI-8",+ "type": "input",+ "description": "Parallel (jam) data input to register stage 8; asynchronous parallel entry when PARALLEL/SERIAL CONTROL is high (CD4021B)."+ },+ {+ "number": "2",+ "name": "Q6",+ "type": "output",+ "description": "Buffered Q output tapped from internal register stage 6."+ },+ {+ "number": "3",+ "name": "Q8",+ "type": "output",+ "description": "Buffered Q output from the final register stage 8 (main serial data output)."+ },+ {+ "number": "4",+ "name": "PI-4",+ "type": "input",+ "description": "Parallel (jam) data input to register stage 4; asynchronous parallel entry when PARALLEL/SERIAL CONTROL is high."+ },+ {+ "number": "5",+ "name": "PI-3",+ "type": "input",+ "description": "Parallel (jam) data input to register stage 3; asynchronous parallel entry when PARALLEL/SERIAL CONTROL is high."+ },+ {+ "number": "6",+ "name": "PI-2",+ "type": "input",+ "description": "Parallel (jam) data input to register stage 2; asynchronous parallel entry when PARALLEL/SERIAL CONTROL is high."+ },+ {+ "number": "7",+ "name": "PI-1",+ "type": "input",+ "description": "Parallel (jam) data input to register stage 1; asynchronous parallel entry when PARALLEL/SERIAL CONTROL is high."+ },+ {+ "number": "8",+ "name": "VSS",+ "type": "power_in",+ "description": "Negative supply / ground return; supply-voltage range VDD to VSS is 3 V to 18 V over the full package-temperature range."+ },+ {+ "number": "9",+ "name": "PARALLEL/SERIAL CONTROL",+ "type": "input",+ "description": "Mode control input: when high, data is asynchronously jammed into the 8-stage register via the parallel inputs; when low, data is shifted in serially, synchronous with the clock's positive transition."+ },+ {+ "number": "10",+ "name": "CLOCK",+ "type": "input",+ "description": "Clock input; register shifts on the positive transition, with maximum clock frequency 3 MHz at VDD=5V, 6 MHz at 10V, and 8.5 MHz at 15V per the recommended operating conditions."+ },+ {+ "number": "11",+ "name": "SERIAL IN",+ "type": "input",+ "description": "Single serial data input; data is shifted into the 8-stage register synchronously with the positive clock transition when PARALLEL/SERIAL CONTROL is low."+ },+ {+ "number": "12",+ "name": "Q7",+ "type": "output",+ "description": "Buffered Q output tapped from internal register stage 7."+ },+ {+ "number": "13",+ "name": "PI-5",+ "type": "input",+ "description": "Parallel (jam) data input to register stage 5; asynchronous parallel entry when PARALLEL/SERIAL CONTROL is high."+ },+ {+ "number": "14",+ "name": "PI-6",+ "type": "input",+ "description": "Parallel (jam) data input to register stage 6; asynchronous parallel entry when PARALLEL/SERIAL CONTROL is high."+ },+ {+ "number": "15",+ "name": "PI-7",+ "type": "input",+ "description": "Parallel (jam) data input to register stage 7; asynchronous parallel entry when PARALLEL/SERIAL CONTROL is high."+ },+ {+ "number": "16",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply pin; supply-voltage range VDD to VSS is 3 V to 18 V over the full package-temperature range."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-sonnet-5",+ "primary_mode": "vision",+ "consensus_model": "claude-opus-4-8",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 12,+ "cost_usd": 0.3642,+ "at": "2026-09-23T20:35:56"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/cd4021b.pdf",+ "pages": 29,+ "sha256": "89a926918808a607",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}