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Initial commit: component/cd4020bmt

Ray ·c6bee77e7f ·
2 files changed +244
README.mdadded+53
@@ -0,0 +1,53 @@+# CD4020BMT++**HGSEMI** · Counters, Dividers · TSSOP-16++CD4020BMT from HGSEMI, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | Q12 | output | Counter stage 12 output from the 14-stage binary counter. |+| 2 | Q13 | output | Counter stage 13 output from the 14-stage binary counter. |+| 3 | Q14 | output | Counter stage 14 output from the 14-stage binary counter. |+| 4 | Q6 | output | Counter stage 6 output from the 14-stage binary counter. |+| 5 | Q5 | output | Counter stage 5 output from the 14-stage binary counter. |+| 6 | Q7 | output | Counter stage 7 output from the 14-stage binary counter. |+| 7 | Q4 | output | Counter stage 4 output from the 14-stage binary counter. |+| 8 | VSS | power_in | Ground; power supply return. |+| 9 | Q1 | output | Counter stage 1 output from the 14-stage binary counter. |+| 10 | φ1 | input | Clock input with Schmitt trigger circuit; counter increments on falling edge. |+| 11 | RESET | input | Reset input; active low; clears all counter outputs. |+| 12 | Q9 | output | Counter stage 9 output from the 14-stage binary counter. |+| 13 | Q8 | output | Counter stage 8 output from the 14-stage binary counter. |+| 14 | Q10 | output | Counter stage 10 output from the 14-stage binary counter. |+| 15 | Q11 | output | Counter stage 11 output from the 14-stage binary counter. |+| 16 | VDD | power_in | Positive power supply voltage; operating range 3.0V to 15.0V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | HGSEMI |+| Package | TSSOP-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CD4020BMT`+- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`+- 3D model: TSSOP-16 (KiCad packages3D, STEP)+- 3D model files: `cd4020bmt-etched.step` / `cd4020bmt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4020bmt.step` / `cd4020bmt.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [HGSEMI datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603087745791107072) (8 pp, sha256 `7f95d7a1ed4cbc4f`, retrieved 2026-09-22, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4020bmt-datasheet.pdf)
page.jsonadded+191
@@ -0,0 +1,191 @@+{+  "slug": "cd4020bmt",+  "version": "0.1.0",+  "type": "component",+  "description": "HGSEMI Counters, Dividers, TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "logic",+    "cd4020bmt",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "cd4020bmt.kicad_sym",+    "cd4020bmt.kicad_mod",+    "cd4020bmt.glb",+    "cd4020bmt.step",+    "cd4020bmt.lbr",+    "docs/hero.png",+    "docs/cd4020bmt-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "component": {+    "mpn": "CD4020BMT",+    "manufacturer": "HGSEMI",+    "package": "TSSOP-16",+    "pin_count": 16,+    "category": "Logic",+    "subcategory": "Counters, Dividers",+    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603087745791107072",+    "parts": {+      "symbol": "cd4020bmt.kicad_sym",+      "footprint": "cd4020bmt.kicad_mod",+      "model_3d": "cd4020bmt-etched.glb",+      "model_3d_plain": "cd4020bmt.glb",+      "model_3d_step": "cd4020bmt-etched.step",+      "model_3d_step_plain": "cd4020bmt.step",+      "lbr": "cd4020bmt.lbr"+    },+    "distributor_links": {+      "lcsc": "C5310817"+    },+    "pins": [+      {+        "number": "1",+        "name": "Q12",+        "type": "output",+        "description": "Counter stage 12 output from the 14-stage binary counter."+      },+      {+        "number": "2",+        "name": "Q13",+        "type": "output",+        "description": "Counter stage 13 output from the 14-stage binary counter."+      },+      {+        "number": "3",+        "name": "Q14",+        "type": "output",+        "description": "Counter stage 14 output from the 14-stage binary counter."+      },+      {+        "number": "4",+        "name": "Q6",+        "type": "output",+        "description": "Counter stage 6 output from the 14-stage binary counter."+      },+      {+        "number": "5",+        "name": "Q5",+        "type": "output",+        "description": "Counter stage 5 output from the 14-stage binary counter."+      },+      {+        "number": "6",+        "name": "Q7",+        "type": "output",+        "description": "Counter stage 7 output from the 14-stage binary counter."+      },+      {+        "number": "7",+        "name": "Q4",+        "type": "output",+        "description": "Counter stage 4 output from the 14-stage binary counter."+      },+      {+        "number": "8",+        "name": "VSS",+        "type": "power_in",+        "description": "Ground; power supply return."+      },+      {+        "number": "9",+        "name": "Q1",+        "type": "output",+        "description": "Counter stage 1 output from the 14-stage binary counter."+      },+      {+        "number": "10",+        "name": "φ1",+        "type": "input",+        "description": "Clock input with Schmitt trigger circuit; counter increments on falling edge."+      },+      {+        "number": "11",+        "name": "RESET",+        "type": "input",+        "description": "Reset input; active low; clears all counter outputs."+      },+      {+        "number": "12",+        "name": "Q9",+        "type": "output",+        "description": "Counter stage 9 output from the 14-stage binary counter."+      },+      {+        "number": "13",+        "name": "Q8",+        "type": "output",+        "description": "Counter stage 8 output from the 14-stage binary counter."+      },+      {+        "number": "14",+        "name": "Q10",+        "type": "output",+        "description": "Counter stage 10 output from the 14-stage binary counter."+      },+      {+        "number": "15",+        "name": "Q11",+        "type": "output",+        "description": "Counter stage 11 output from the 14-stage binary counter."+      },+      {+        "number": "16",+        "name": "VDD",+        "type": "power_in",+        "description": "Positive power supply voltage; operating range 3.0V to 15.0V."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.2",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.2",+        "primary_model": "claude-haiku-4-5-20251001",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-4-6",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [+          "1/16 pin names appear NOWHERE in the datasheet text: ['10:φ1@p2']"+        ],+        "pages_sent": 8,+        "cost_usd": 0.1605,+        "at": "2026-09-22T08:58:10"+      },+      "datasheet": {+        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603087745791107072",+        "pages": 8,+        "sha256": "7f95d7a1ed4cbc4f",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 16,+        "described": 16,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file