CD4019BM96

@@ -53,97 +53,97 @@         "number": "1",         "name": "B4",         "type": "input",-        "description": "Channel-B data input to AND/OR select gate 4, contributing to output D4 = A4\u00b7Ka + B4\u00b7Kb; CMOS-protected input."+        "description": "Channel-B data input to AND/OR select gate 4, contributing to output D4 = A4·Ka + B4·Kb; CMOS-protected input."       },       {         "number": "2",         "name": "A3",         "type": "input",-        "description": "Channel-A data input to AND/OR select gate 3, contributing to output D3 = A3\u00b7Ka + B3\u00b7Kb; CMOS-protected input."+        "description": "Channel-A data input to AND/OR select gate 3, contributing to output D3 = A3·Ka + B3·Kb; CMOS-protected input."       },       {         "number": "3",         "name": "B3",         "type": "input",-        "description": "Channel-B data input to AND/OR select gate 3, contributing to output D3 = A3\u00b7Ka + B3\u00b7Kb; CMOS-protected input."+        "description": "Channel-B data input to AND/OR select gate 3, contributing to output D3 = A3·Ka + B3·Kb; CMOS-protected input."       },       {         "number": "4",         "name": "A2",         "type": "input",-        "description": "Channel-A data input to AND/OR select gate 2, contributing to output D2 = A2\u00b7Ka + B2\u00b7Kb; CMOS-protected input."+        "description": "Channel-A data input to AND/OR select gate 2, contributing to output D2 = A2·Ka + B2·Kb; CMOS-protected input."       },       {         "number": "5",         "name": "B2",         "type": "input",-        "description": "Channel-B data input to AND/OR select gate 2, contributing to output D2 = A2\u00b7Ka + B2\u00b7Kb; CMOS-protected input."+        "description": "Channel-B data input to AND/OR select gate 2, contributing to output D2 = A2·Ka + B2·Kb; CMOS-protected input."       },       {         "number": "6",         "name": "A1",         "type": "input",-        "description": "Channel-A data input to AND/OR select gate 1, contributing to output D1 = A1\u00b7Ka + B1\u00b7Kb; CMOS-protected input."+        "description": "Channel-A data input to AND/OR select gate 1, contributing to output D1 = A1·Ka + B1·Kb; CMOS-protected input."       },       {         "number": "7",         "name": "B1",         "type": "input",-        "description": "Channel-B data input to AND/OR select gate 1, contributing to output D1 = A1\u00b7Ka + B1\u00b7Kb; CMOS-protected input."+        "description": "Channel-B data input to AND/OR select gate 1, contributing to output D1 = A1·Ka + B1·Kb; CMOS-protected input."       },       {         "number": "8",         "name": "VSS",         "type": "power_in",-        "description": "Negative supply/ground reference terminal; DC supply voltage VDD is referenced to VSS over a \u22120.5 V to +20 V range."+        "description": "Negative supply/ground reference terminal; DC supply voltage VDD is referenced to VSS over a −0.5 V to +20 V range."       },       {         "number": "9",         "name": "Ka",         "type": "input",-        "description": "Common control-bit input that selects channel A data (A1-A4) for all four select gates; CMOS-protected input, max input current 1 \u00b5A at 18 V over full temperature range."+        "description": "Common control-bit input that selects channel A data (A1-A4) for all four select gates; CMOS-protected input, max input current 1 µA at 18 V over full temperature range."       },       {         "number": "10",         "name": "D1",         "type": "output",-        "description": "Select-gate 1 output, D1 = A1\u00b7Ka + B1\u00b7Kb, driven by the internal AND/OR logic with symmetrical output characteristics."+        "description": "Select-gate 1 output, D1 = A1·Ka + B1·Kb, driven by the internal AND/OR logic with symmetrical output characteristics."       },       {         "number": "11",         "name": "D2",         "type": "output",-        "description": "Select-gate 2 output, D2 = A2\u00b7Ka + B2\u00b7Kb, driven by the internal AND/OR logic with symmetrical output characteristics."+        "description": "Select-gate 2 output, D2 = A2·Ka + B2·Kb, driven by the internal AND/OR logic with symmetrical output characteristics."       },       {         "number": "12",         "name": "D3",         "type": "output",-        "description": "Select-gate 3 output, D3 = A3\u00b7Ka + B3\u00b7Kb, driven by the internal AND/OR logic with symmetrical output characteristics."+        "description": "Select-gate 3 output, D3 = A3·Ka + B3·Kb, driven by the internal AND/OR logic with symmetrical output characteristics."       },       {         "number": "13",         "name": "D4",         "type": "output",-        "description": "Select-gate 4 output, D4 = A4\u00b7Ka + B4\u00b7Kb, driven by the internal AND/OR logic with symmetrical output characteristics."+        "description": "Select-gate 4 output, D4 = A4·Ka + B4·Kb, driven by the internal AND/OR logic with symmetrical output characteristics."       },       {         "number": "14",         "name": "Kb",         "type": "input",-        "description": "Common control-bit input that selects channel B data (B1-B4) for all four select gates; CMOS-protected input, max input current 1 \u00b5A at 18 V over full temperature range."+        "description": "Common control-bit input that selects channel B data (B1-B4) for all four select gates; CMOS-protected input, max input current 1 µA at 18 V over full temperature range."       },       {         "number": "15",         "name": "A4",         "type": "input",-        "description": "Channel-A data input to AND/OR select gate 4, contributing to output D4 = A4\u00b7Ka + B4\u00b7Kb; CMOS-protected input."+        "description": "Channel-A data input to AND/OR select gate 4, contributing to output D4 = A4·Ka + B4·Kb; CMOS-protected input."       },       {         "number": "16",         "name": "VDD",         "type": "power_in",-        "description": "Positive DC supply voltage terminal, referenced to VSS, rated \u22120.5 V to +20 V absolute maximum and 3 V to 18 V recommended over full package temperature range."+        "description": "Positive DC supply voltage terminal, referenced to VSS, rated −0.5 V to +20 V absolute maximum and 3 V to 18 V recommended over full package temperature range."       }     ],     "provenance": {@@ -180,6 +180,46 @@     "viewers": {       "symbol": "viewers/symbol.html",       "footprint": "viewers/footprint.html"-    }+    },+    "models_3d": [+      {+        "file": "cd4019bm96.step",+        "role": "plain",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          6.0,+          9.9,+          1.75+        ],+        "zmin_mm": -0.0,+        "centre_offset_mm": 0.0,+        "footprint_binding": "identity",+        "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",+        "checked": "2026-10-07",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      },+      {+        "file": "cd4019bm96-etched.step",+        "role": "eda",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          6.0,+          9.9,+          1.75+        ],+        "zmin_mm": -0.0,+        "centre_offset_mm": 0.0,+        "footprint_binding": "identity",+        "sha256": "0d4fe5c8bee9e196587a0f9fec56a1fd155ea97e9cd81d725203026ee687f7d5",+        "checked": "2026-10-07",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      }+    ]   }-}\ No newline at end of file+}