component
CD4019BM96
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# CD4019BM96++**Texas Instruments** · Logic Gates · SOIC-16++CD4019BM96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | B4 | input | Channel-B data input to AND/OR select gate 4, contributing to output D4 = A4·Ka + B4·Kb; CMOS-protected input. |+| 2 | A3 | input | Channel-A data input to AND/OR select gate 3, contributing to output D3 = A3·Ka + B3·Kb; CMOS-protected input. |+| 3 | B3 | input | Channel-B data input to AND/OR select gate 3, contributing to output D3 = A3·Ka + B3·Kb; CMOS-protected input. |+| 4 | A2 | input | Channel-A data input to AND/OR select gate 2, contributing to output D2 = A2·Ka + B2·Kb; CMOS-protected input. |+| 5 | B2 | input | Channel-B data input to AND/OR select gate 2, contributing to output D2 = A2·Ka + B2·Kb; CMOS-protected input. |+| 6 | A1 | input | Channel-A data input to AND/OR select gate 1, contributing to output D1 = A1·Ka + B1·Kb; CMOS-protected input. |+| 7 | B1 | input | Channel-B data input to AND/OR select gate 1, contributing to output D1 = A1·Ka + B1·Kb; CMOS-protected input. |+| 8 | VSS | power_in | Negative supply/ground reference terminal; DC supply voltage VDD is referenced to VSS over a −0.5 V to +20 V range. |+| 9 | Ka | input | Common control-bit input that selects channel A data (A1-A4) for all four select gates; CMOS-protected input, max input current 1 µA at 18 V over full temperature range. |+| 10 | D1 | output | Select-gate 1 output, D1 = A1·Ka + B1·Kb, driven by the internal AND/OR logic with symmetrical output characteristics. |+| 11 | D2 | output | Select-gate 2 output, D2 = A2·Ka + B2·Kb, driven by the internal AND/OR logic with symmetrical output characteristics. |+| 12 | D3 | output | Select-gate 3 output, D3 = A3·Ka + B3·Kb, driven by the internal AND/OR logic with symmetrical output characteristics. |+| 13 | D4 | output | Select-gate 4 output, D4 = A4·Ka + B4·Kb, driven by the internal AND/OR logic with symmetrical output characteristics. |+| 14 | Kb | input | Common control-bit input that selects channel B data (B1-B4) for all four select gates; CMOS-protected input, max input current 1 µA at 18 V over full temperature range. |+| 15 | A4 | input | Channel-A data input to AND/OR select gate 4, contributing to output D4 = A4·Ka + B4·Kb; CMOS-protected input. |+| 16 | VDD | power_in | Positive DC supply voltage terminal, referenced to VSS, rated −0.5 V to +20 V absolute maximum and 3 V to 18 V recommended over full package temperature range. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CD4019BM96`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)+- 3D model files: `cd4019bm96-etched.step` / `cd4019bm96-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4019bm96.step` / `cd4019bm96.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd4019b) (19 pp, sha256 `97c4321a9ad89a2e`, retrieved 2026-09-23, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-sonnet-5` (text+vision), consensus `claude-opus-4-8` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4019bm96-datasheet.pdf)
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CMOS-protected input."+ },+ {+ "number": "2",+ "name": "A3",+ "type": "input",+ "description": "Channel-A data input to AND/OR select gate 3, contributing to output D3 = A3·Ka + B3·Kb; CMOS-protected input."+ },+ {+ "number": "3",+ "name": "B3",+ "type": "input",+ "description": "Channel-B data input to AND/OR select gate 3, contributing to output D3 = A3·Ka + B3·Kb; CMOS-protected input."+ },+ {+ "number": "4",+ "name": "A2",+ "type": "input",+ "description": "Channel-A data input to AND/OR select gate 2, contributing to output D2 = A2·Ka + B2·Kb; CMOS-protected input."+ },+ {+ "number": "5",+ "name": "B2",+ "type": "input",+ "description": "Channel-B data input to AND/OR select gate 2, contributing to output D2 = A2·Ka + B2·Kb; CMOS-protected input."+ },+ {+ "number": "6",+ "name": "A1",+ "type": "input",+ "description": "Channel-A data input to AND/OR select gate 1, contributing to output D1 = A1·Ka + B1·Kb; CMOS-protected input."+ },+ {+ "number": "7",+ "name": "B1",+ "type": "input",+ "description": "Channel-B data input to AND/OR select gate 1, contributing to output D1 = A1·Ka + B1·Kb; CMOS-protected input."+ },+ {+ "number": "8",+ "name": "VSS",+ "type": "power_in",+ "description": "Negative supply/ground reference terminal; DC supply voltage VDD is referenced to VSS over a −0.5 V to +20 V range."+ },+ {+ "number": "9",+ "name": "Ka",+ "type": "input",+ "description": "Common control-bit input that selects channel A data (A1-A4) for all four select gates; CMOS-protected input, max input current 1 µA at 18 V over full temperature range."+ },+ {+ "number": "10",+ "name": "D1",+ "type": "output",+ "description": "Select-gate 1 output, D1 = A1·Ka + B1·Kb, driven by the internal AND/OR logic with symmetrical output characteristics."+ },+ {+ "number": "11",+ "name": "D2",+ "type": "output",+ "description": "Select-gate 2 output, D2 = A2·Ka + B2·Kb, driven by the internal AND/OR logic with symmetrical output characteristics."+ },+ {+ "number": "12",+ "name": "D3",+ "type": "output",+ "description": "Select-gate 3 output, D3 = A3·Ka + B3·Kb, driven by the internal AND/OR logic with symmetrical output characteristics."+ },+ {+ "number": "13",+ "name": "D4",+ "type": "output",+ "description": "Select-gate 4 output, D4 = A4·Ka + B4·Kb, driven by the internal AND/OR logic with symmetrical output characteristics."+ },+ {+ "number": "14",+ "name": "Kb",+ "type": "input",+ "description": "Common control-bit input that selects channel B data (B1-B4) for all four select gates; CMOS-protected input, max input current 1 µA at 18 V over full temperature range."+ },+ {+ "number": "15",+ "name": "A4",+ "type": "input",+ "description": "Channel-A data input to AND/OR select gate 4, contributing to output D4 = A4·Ka + B4·Kb; CMOS-protected input."+ },+ {+ "number": "16",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive DC supply voltage terminal, referenced to VSS, rated −0.5 V to +20 V absolute maximum and 3 V to 18 V recommended over full package temperature range."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-sonnet-5",+ "primary_mode": "text+vision",+ "consensus_model": "claude-opus-4-8",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 19,+ "cost_usd": 0.5687,+ "at": "2026-09-23T00:22:35"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cd4019b",+ "pages": 19,+ "sha256": "97c4321a9ad89a2e",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}