CD4013S

@@ -0,0 +1,55 @@+# CD4013S++**GR** · Flip Flops · SOP-14++CD4013S from GR, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | Q1 | output | Non-inverting (Q) output of flip-flop 1. Buffered CMOS output; follows the D1 input on the rising edge of CLOCK1. |+| 2 | Q1_N | output | Inverting (Q-bar) output of flip-flop 1. Complement of Q1. |+| 3 | CLOCK1 | input | Clock input for flip-flop 1. D1 is latched to Q1 on the rising (positive) edge of this signal. |+| 4 | RESET1 | input | Asynchronous active-high reset for flip-flop 1. When high, forces Q1 low and Q1_N high, independent of CLOCK1. |+| 5 | D1 | input | Data input for flip-flop 1. Logic level present at D1 is transferred to Q1 on the rising edge of CLOCK1. |+| 6 | SET1 | input | Asynchronous active-high set for flip-flop 1. When high, forces Q1 high and Q1_N low, independent of CLOCK1. |+| 7 | VSS | power_in | Negative supply / ground reference (0 V). Connect to system ground. |+| 8 | SET2 | input | Asynchronous active-high set for flip-flop 2. When high, forces Q2 high and Q2_N low, independent of CLOCK2. |+| 9 | D2 | input | Data input for flip-flop 2. Logic level present at D2 is transferred to Q2 on the rising edge of CLOCK2. |+| 10 | RESET2 | input | Asynchronous active-high reset for flip-flop 2. When high, forces Q2 low and Q2_N high, independent of CLOCK2. |+| 11 | CLOCK2 | input | Clock input for flip-flop 2. D2 is latched to Q2 on the rising (positive) edge of this signal. |+| 12 | Q2_N | output | Inverting (Q-bar) output of flip-flop 2. Complement of Q2. |+| 13 | Q2 | output | Non-inverting (Q) output of flip-flop 2. Buffered CMOS output; follows the D2 input on the rising edge of CLOCK2. |+| 14 | VDD | power_in | Positive supply voltage. Operating range 3.0 V to 15.0 V; absolute maximum -0.5 V to +18 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | GR |+| Package | SOP-14 |+| Category | Logic |+| Pins | 14 |++## Ordering variants++- `CD4013SS`+- `CD4013SD`++## CAD (KiCad official)++- Symbol: `CD4013S`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOP-14 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [GR datasheet](docs/cd4013s-datasheet.pdf) (6 pp, sha256 `64b756b2aee27e59`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4013s-datasheet.pdf)

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