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cd4013s: factory component page (tier=lcsc)

Ray ·1695a70dac · ·parent 3189cba
1 file changed +152−8
page.json+152−8
@@ -1,13 +1,162 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "cd4013s",+  "title": "CD4013S",+  "brief": "GR Flip Flops, SOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",-  "type": "component",-  "description": "GR Flip Flops, SOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "logic",     "cd4013s"   ],+  "component": {+    "mpn": "CD4013S",+    "manufacturer": "GR",+    "package": "SOP-14",+    "pin_count": 14,+    "category": "Logic",+    "subcategory": "Flip Flops",+    "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2312261746_GR-CD4013S_C19818873.pdf",+    "parts": {+      "symbol": "cd4013s.kicad_sym",+      "footprint": "cd4013s.kicad_mod",+      "model_3d": "cd4013s.glb",+      "model_3d_step": "cd4013s.step",+      "lbr": "cd4013s.lbr"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "Q1",+        "type": "output",+        "description": "Non-inverting (Q) output of flip-flop 1. Buffered CMOS output; follows the D1 input on the rising edge of CLOCK1."+      },+      {+        "number": "2",+        "name": "Q1_N",+        "type": "output",+        "description": "Inverting (Q-bar) output of flip-flop 1. Complement of Q1."+      },+      {+        "number": "3",+        "name": "CLOCK1",+        "type": "input",+        "description": "Clock input for flip-flop 1. D1 is latched to Q1 on the rising (positive) edge of this signal."+      },+      {+        "number": "4",+        "name": "RESET1",+        "type": "input",+        "description": "Asynchronous active-high reset for flip-flop 1. When high, forces Q1 low and Q1_N high, independent of CLOCK1."+      },+      {+        "number": "5",+        "name": "D1",+        "type": "input",+        "description": "Data input for flip-flop 1. Logic level present at D1 is transferred to Q1 on the rising edge of CLOCK1."+      },+      {+        "number": "6",+        "name": "SET1",+        "type": "input",+        "description": "Asynchronous active-high set for flip-flop 1. When high, forces Q1 high and Q1_N low, independent of CLOCK1."+      },+      {+        "number": "7",+        "name": "VSS",+        "type": "power_in",+        "description": "Negative supply / ground reference (0 V). Connect to system ground."+      },+      {+        "number": "8",+        "name": "SET2",+        "type": "input",+        "description": "Asynchronous active-high set for flip-flop 2. When high, forces Q2 high and Q2_N low, independent of CLOCK2."+      },+      {+        "number": "9",+        "name": "D2",+        "type": "input",+        "description": "Data input for flip-flop 2. Logic level present at D2 is transferred to Q2 on the rising edge of CLOCK2."+      },+      {+        "number": "10",+        "name": "RESET2",+        "type": "input",+        "description": "Asynchronous active-high reset for flip-flop 2. When high, forces Q2 low and Q2_N high, independent of CLOCK2."+      },+      {+        "number": "11",+        "name": "CLOCK2",+        "type": "input",+        "description": "Clock input for flip-flop 2. D2 is latched to Q2 on the rising (positive) edge of this signal."+      },+      {+        "number": "12",+        "name": "Q2_N",+        "type": "output",+        "description": "Inverting (Q-bar) output of flip-flop 2. Complement of Q2."+      },+      {+        "number": "13",+        "name": "Q2",+        "type": "output",+        "description": "Non-inverting (Q) output of flip-flop 2. Buffered CMOS output; follows the D2 input on the rising edge of CLOCK2."+      },+      {+        "number": "14",+        "name": "VDD",+        "type": "power_in",+        "description": "Positive supply voltage. Operating range 3.0 V to 15.0 V; absolute maximum -0.5 V to +18 V."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2312261746_GR-CD4013S_C19818873.pdf",+        "pages": 6,+        "sha256": "64b756b2aee27e59",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 14,+        "described": 14,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Manufacturer": "GR",+      "Package": "SOP-14",+      "Category": "Logic",+      "Pins": "14"+    }+  },+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "cd4013s"+  ],+  "discovery_pitch": "CD4013S (GR) component page with datasheet-verified CAD.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -25,10 +174,5 @@     "docs/cd4013s-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file