CD4012B Dual NAND Gate

@@ -0,0 +1,63 @@+# CD4012B++**Texas Instruments** · Logic Gate · SOIC-14++The CD4012B contains two independent 4-input NAND gates; each output is low only when all four inputs are high. It runs from 3 V to 18 V, part of the 4000B CMOS logic family.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | J | output | Gate 1 NAND output. J = NOT(A AND B AND C AND D). CMOS output rail-to-rail; sinks/sources ~1 mA at VDD = 5 V. |+| 2 | A | input | Gate 1 NAND input A. High-impedance CMOS input protected by an internal ESD network; VIH = 3.5 V min at VDD = 5 V. |+| 3 | B | input | Gate 1 NAND input B. High-impedance CMOS input protected by an internal ESD network. |+| 4 | C | input | Gate 1 NAND input C. High-impedance CMOS input protected by an internal ESD network. |+| 5 | D | input | Gate 1 NAND input D. High-impedance CMOS input protected by an internal ESD network. |+| 6 | NC | unconnected | No internal connection. Leave floating or tie to VDD/VSS as convenient; datasheet notes NC = no connection. |+| 7 | VSS | power_in | Negative supply / ground reference. Connect to 0 V. All input/output voltages are referenced to VSS. |+| 8 | NC | unconnected | No internal connection. Leave floating or tie to VDD/VSS as convenient. |+| 9 | E | input | Gate 2 NAND input E. High-impedance CMOS input protected by an internal ESD network. |+| 10 | F | input | Gate 2 NAND input F. High-impedance CMOS input protected by an internal ESD network. |+| 11 | G | input | Gate 2 NAND input G. High-impedance CMOS input protected by an internal ESD network. |+| 12 | H | input | Gate 2 NAND input H. High-impedance CMOS input protected by an internal ESD network. |+| 13 | K | output | Gate 2 NAND output. K = NOT(E AND F AND G AND H). CMOS output rail-to-rail; sinks/sources ~1 mA at VDD = 5 V. |+| 14 | VDD | power_in | Positive supply. Operating range 3 V to 18 V (recommended); absolute maximum 20 V referenced to VSS. Bypass locally with 100 nF ceramic. |++## Key specifications++| Parameter | Value |+|---|---|+| Type | Dual NAND Gate |+| Logic family | 4000B (CMOS) |+| Supply voltage | 3 V to 18 V |+| Propagation delay | 50 ns typ at 10 V |+| Operating temperature | -55 C to 125 C |++## Ordering variants++- `CD4012BM`+- `CD4012BM96`+- `CD4012BME4`+- `CD4012BM96E4`+- `CD4012BE`+- `CD4012BEE4`+- `CD4012BF3A`+- `CD4012BF3A.A`+- `CD4012BNSR`+- `CD4012BPWR`++## CAD (KiCad official)++- Symbol: `cd4012.kicad_sym`+- Footprint: `cd4012.kicad_mod`+- 3D model: SOIC-14 body from KiCad `Package_SO/SOIC-14_3.9x8.7mm_P1.27mm`.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd4012b.pdf) (23 pp, sha256 `92d82fa35555e4e4`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4012-datasheet.pdf)

@@ -0,0 +1,36 @@+{+  "slug": "cd4012",+  "version": "0.1.0",+  "type": "component",+  "description": "Dual NAND Gate in the 4000B CMOS family, 3 V to 18 V.",+  "tags": [+    "logic",+    "gate",+    "4000-series",+    "cmos",+    "ti",+    "soic-14"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "cd4012.kicad_sym",+    "cd4012.kicad_mod",+    "cd4012.glb",+    "cd4012.step",+    "docs/hero.png",+    "docs/cd4012-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file