component
CD4012B Dual NAND Gate
Public Made by Adomby adom
Dual NAND Gate in the 4000B CMOS family, 3 V to 18 V.
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page.json+155−8@@ -1,8 +1,11 @@ {+ "schema_version": 1,+ "type": "component", "slug": "cd4012",+ "title": "CD4012B Dual NAND Gate",+ "brief": "Dual NAND Gate in the 4000B CMOS family, 3 V to 18 V.", "version": "0.1.0",- "type": "component",- "description": "Dual NAND Gate in the 4000B CMOS family, 3 V to 18 V.",+ "license": "CC-BY-SA-4.0", "tags": [ "logic", "gate",@@ -11,6 +14,155 @@ "ti", "soic-14" ],+ "component": {+ "mpn": "CD4012B",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-14",+ "pin_count": 14,+ "category": "Logic",+ "subcategory": "Logic Gate",+ "datasheet": "https://www.ti.com/lit/ds/symlink/cd4012b.pdf",+ "parts": {+ "symbol": "cd4012.kicad_sym",+ "footprint": "cd4012.kicad_mod",+ "model_3d": "cd4012.glb",+ "model_3d_step": "cd4012.step"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "J",+ "type": "output",+ "description": "Gate 1 NAND output. J = NOT(A AND B AND C AND D). CMOS output rail-to-rail; sinks/sources ~1 mA at VDD = 5 V."+ },+ {+ "number": "2",+ "name": "A",+ "type": "input",+ "description": "Gate 1 NAND input A. High-impedance CMOS input protected by an internal ESD network; VIH = 3.5 V min at VDD = 5 V."+ },+ {+ "number": "3",+ "name": "B",+ "type": "input",+ "description": "Gate 1 NAND input B. High-impedance CMOS input protected by an internal ESD network."+ },+ {+ "number": "4",+ "name": "C",+ "type": "input",+ "description": "Gate 1 NAND input C. High-impedance CMOS input protected by an internal ESD network."+ },+ {+ "number": "5",+ "name": "D",+ "type": "input",+ "description": "Gate 1 NAND input D. High-impedance CMOS input protected by an internal ESD network."+ },+ {+ "number": "6",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection. Leave floating or tie to VDD/VSS as convenient; datasheet notes NC = no connection."+ },+ {+ "number": "7",+ "name": "VSS",+ "type": "power_in",+ "description": "Negative supply / ground reference. Connect to 0 V. All input/output voltages are referenced to VSS."+ },+ {+ "number": "8",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection. Leave floating or tie to VDD/VSS as convenient."+ },+ {+ "number": "9",+ "name": "E",+ "type": "input",+ "description": "Gate 2 NAND input E. High-impedance CMOS input protected by an internal ESD network."+ },+ {+ "number": "10",+ "name": "F",+ "type": "input",+ "description": "Gate 2 NAND input F. High-impedance CMOS input protected by an internal ESD network."+ },+ {+ "number": "11",+ "name": "G",+ "type": "input",+ "description": "Gate 2 NAND input G. High-impedance CMOS input protected by an internal ESD network."+ },+ {+ "number": "12",+ "name": "H",+ "type": "input",+ "description": "Gate 2 NAND input H. High-impedance CMOS input protected by an internal ESD network."+ },+ {+ "number": "13",+ "name": "K",+ "type": "output",+ "description": "Gate 2 NAND output. K = NOT(E AND F AND G AND H). CMOS output rail-to-rail; sinks/sources ~1 mA at VDD = 5 V."+ },+ {+ "number": "14",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply. Operating range 3 V to 18 V (recommended); absolute maximum 20 V referenced to VSS. Bypass locally with 100 nF ceramic."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/cd4012b.pdf",+ "pages": 23,+ "sha256": "92d82fa35555e4e4",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Type": "Dual NAND Gate",+ "Logic family": "4000B (CMOS)",+ "Supply voltage": "3 V to 18 V",+ "Propagation delay": "50 ns typ at 10 V",+ "Operating temperature": "-55 C to 125 C"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "Dual NAND Gate",+ "CMOS logic",+ "wide-voltage logic",+ "glue logic"+ ],+ "discovery_pitch": "The CD4012B contains two independent 4-input NAND gates; each output is low only when all four inputs are high.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -27,10 +179,5 @@ "docs/cd4012-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }