component
CD4011UBM96
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.
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README.mdadded+50@@ -0,0 +1,50 @@+# CD4011UBM96++**Texas Instruments** · Logic Gates · SOIC-14++CD4011UBM96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | A | input | Input A to NAND gate 1 (with input B, output J); input voltage range -0.5V to VDD+0.5V, max DC input current ±10mA. |+| 2 | B | input | Input B to NAND gate 1 (with input A, output J); input voltage range -0.5V to VDD+0.5V, max DC input current ±10mA. |+| 3 | J | output | Output of NAND gate 1, J = NOT(A AND B). |+| 4 | K | output | Output of NAND gate 2, K = NOT(C AND D). |+| 5 | C | input | Input C to NAND gate 2 (with input D, output K); input voltage range -0.5V to VDD+0.5V, max DC input current ±10mA. |+| 6 | D | input | Input D to NAND gate 2 (with input C, output K); input voltage range -0.5V to VDD+0.5V, max DC input current ±10mA. |+| 7 | VSS | power_in | Negative supply / ground reference terminal, all voltages referenced to VSS. |+| 8 | E | input | Input E to NAND gate 3 (with input F, output L); input voltage range -0.5V to VDD+0.5V, max DC input current ±10mA. |+| 9 | F | input | Input F to NAND gate 3 (with input E, output L); input voltage range -0.5V to VDD+0.5V, max DC input current ±10mA. |+| 10 | L | output | Output of NAND gate 3, L = NOT(E AND F). |+| 11 | M | output | Output of NAND gate 4, M = NOT(G AND H). |+| 12 | G | input | Input G to NAND gate 4 (with input H, output M); input voltage range -0.5V to VDD+0.5V, max DC input current ±10mA. |+| 13 | H | input | Input H to NAND gate 4 (with input G, output M); input voltage range -0.5V to VDD+0.5V, max DC input current ±10mA. |+| 14 | VDD | power_in | Positive supply voltage, absolute maximum -0.5V to +20V referenced to VSS, recommended operating range 3V to 18V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-14 |+| Category | Logic |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `CD4011UBM96`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D, STEP)+- 3D model files: `cd4011ubm96-etched.step` / `cd4011ubm96-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4011ubm96.step` / `cd4011ubm96.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd4011ub) (20 pp, sha256 `62907fabea7494c9`, retrieved 2026-09-23, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-sonnet-5` (text+vision), consensus `claude-opus-4-8` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4011ubm96-datasheet.pdf)
page.jsonadded+179@@ -0,0 +1,179 @@+{+ "slug": "cd4011ubm96",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Logic Gates, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "cd4011ubm96",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cd4011ubm96.kicad_sym",+ "cd4011ubm96.kicad_mod",+ "cd4011ubm96.glb",+ "cd4011ubm96.step",+ "cd4011ubm96.lbr",+ "docs/hero.png",+ "docs/cd4011ubm96-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "CD4011UBM96",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-14",+ "pin_count": 14,+ "category": "Logic",+ "subcategory": "Logic Gates",+ "datasheet": "https://www.ti.com/cn/lit/gpn/cd4011ub",+ "parts": {+ "symbol": "cd4011ubm96.kicad_sym",+ "footprint": "cd4011ubm96.kicad_mod",+ "model_3d": "cd4011ubm96-etched.glb",+ "model_3d_plain": "cd4011ubm96.glb",+ "model_3d_step": "cd4011ubm96-etched.step",+ "model_3d_step_plain": "cd4011ubm96.step",+ "lbr": "cd4011ubm96.lbr"+ },+ "distributor_links": {+ "lcsc": "C2865390"+ },+ "pins": [+ {+ "number": "1",+ "name": "A",+ "type": "input",+ "description": "Input A to NAND gate 1 (with input B, output J); input voltage range -0.5V to VDD+0.5V, max DC input current ±10mA."+ },+ {+ "number": "2",+ "name": "B",+ "type": "input",+ "description": "Input B to NAND gate 1 (with input A, output J); input voltage range -0.5V to VDD+0.5V, max DC input current ±10mA."+ },+ {+ "number": "3",+ "name": "J",+ "type": "output",+ "description": "Output of NAND gate 1, J = NOT(A AND B)."+ },+ {+ "number": "4",+ "name": "K",+ "type": "output",+ "description": "Output of NAND gate 2, K = NOT(C AND D)."+ },+ {+ "number": "5",+ "name": "C",+ "type": "input",+ "description": "Input C to NAND gate 2 (with input D, output K); input voltage range -0.5V to VDD+0.5V, max DC input current ±10mA."+ },+ {+ "number": "6",+ "name": "D",+ "type": "input",+ "description": "Input D to NAND gate 2 (with input C, output K); input voltage range -0.5V to VDD+0.5V, max DC input current ±10mA."+ },+ {+ "number": "7",+ "name": "VSS",+ "type": "power_in",+ "description": "Negative supply / ground reference terminal, all voltages referenced to VSS."+ },+ {+ "number": "8",+ "name": "E",+ "type": "input",+ "description": "Input E to NAND gate 3 (with input F, output L); input voltage range -0.5V to VDD+0.5V, max DC input current ±10mA."+ },+ {+ "number": "9",+ "name": "F",+ "type": "input",+ "description": "Input F to NAND gate 3 (with input E, output L); input voltage range -0.5V to VDD+0.5V, max DC input current ±10mA."+ },+ {+ "number": "10",+ "name": "L",+ "type": "output",+ "description": "Output of NAND gate 3, L = NOT(E AND F)."+ },+ {+ "number": "11",+ "name": "M",+ "type": "output",+ "description": "Output of NAND gate 4, M = NOT(G AND H)."+ },+ {+ "number": "12",+ "name": "G",+ "type": "input",+ "description": "Input G to NAND gate 4 (with input H, output M); input voltage range -0.5V to VDD+0.5V, max DC input current ±10mA."+ },+ {+ "number": "13",+ "name": "H",+ "type": "input",+ "description": "Input H to NAND gate 4 (with input G, output M); input voltage range -0.5V to VDD+0.5V, max DC input current ±10mA."+ },+ {+ "number": "14",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply voltage, absolute maximum -0.5V to +20V referenced to VSS, recommended operating range 3V to 18V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-sonnet-5",+ "primary_mode": "text+vision",+ "consensus_model": "claude-opus-4-8",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 20,+ "cost_usd": 0.623,+ "at": "2026-09-23T22:19:56"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cd4011ub",+ "pages": 20,+ "sha256": "62907fabea7494c9",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}