component
CD4011S
Public Made by Adomby adom
GR Gates, SOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+152−8@@ -1,13 +1,162 @@ {+ "schema_version": 1,+ "type": "component", "slug": "cd4011s",+ "title": "CD4011S",+ "brief": "GR Gates, SOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "GR Gates, SOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic", "cd4011s" ],+ "component": {+ "mpn": "CD4011S",+ "manufacturer": "GR",+ "package": "SOP-14",+ "pin_count": 14,+ "category": "Logic",+ "subcategory": "Gates",+ "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2312261746_GR-CD4011S_C19818878.pdf",+ "parts": {+ "symbol": "cd4011s.kicad_sym",+ "footprint": "cd4011s.kicad_mod",+ "model_3d": "cd4011s.glb",+ "model_3d_step": "cd4011s.step",+ "lbr": "cd4011s.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "A1",+ "type": "input",+ "description": "Input A of NAND gate 1. CMOS logic input; VIH>=3.5V @ VDD=5V, VIL<=1.5V @ VDD=5V. Input current <= 1uA."+ },+ {+ "number": "2",+ "name": "B1",+ "type": "input",+ "description": "Input B of NAND gate 1. CMOS logic input paired with A1."+ },+ {+ "number": "3",+ "name": "Y1",+ "type": "output",+ "description": "Output of NAND gate 1: Y1 = NAND(A1, B1). VOH >= 4.95V @ VDD=5V (|IOUT|<1uA); typical sourcing -1.0mA @ Vo=4.6V, sinking 2.2mA @ Vo=0.4V."+ },+ {+ "number": "4",+ "name": "Y2",+ "type": "output",+ "description": "Output of NAND gate 2: Y2 = NAND(A2, B2). Same drive characteristics as Y1."+ },+ {+ "number": "5",+ "name": "A2",+ "type": "input",+ "description": "Input A of NAND gate 2. CMOS logic input."+ },+ {+ "number": "6",+ "name": "B2",+ "type": "input",+ "description": "Input B of NAND gate 2. CMOS logic input paired with A2."+ },+ {+ "number": "7",+ "name": "VSS",+ "type": "power_in",+ "description": "Negative supply / ground reference (0V). Absolute maximum VDD-VSS = 18V."+ },+ {+ "number": "8",+ "name": "A3",+ "type": "input",+ "description": "Input A of NAND gate 3. CMOS logic input."+ },+ {+ "number": "9",+ "name": "B3",+ "type": "input",+ "description": "Input B of NAND gate 3. CMOS logic input paired with A3."+ },+ {+ "number": "10",+ "name": "Y3",+ "type": "output",+ "description": "Output of NAND gate 3: Y3 = NAND(A3, B3)."+ },+ {+ "number": "11",+ "name": "Y4",+ "type": "output",+ "description": "Output of NAND gate 4: Y4 = NAND(A4, B4)."+ },+ {+ "number": "12",+ "name": "A4",+ "type": "input",+ "description": "Input A of NAND gate 4. CMOS logic input."+ },+ {+ "number": "13",+ "name": "B4",+ "type": "input",+ "description": "Input B of NAND gate 4. CMOS logic input paired with A4."+ },+ {+ "number": "14",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply. Recommended 2.5V to 15V; absolute maximum -0.5V to +18V referenced to VSS."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2312261746_GR-CD4011S_C19818878.pdf",+ "pages": 5,+ "sha256": "c6ad9d7e0313c497",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "GR",+ "Package": "SOP-14",+ "Category": "Logic",+ "Pins": "14"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "cd4011s"+ ],+ "discovery_pitch": "CD4011S (GR) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +174,5 @@ "docs/cd4011s-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }