component
CD4011S
Public Made by Adomby adom
GR Gates, SOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+55@@ -0,0 +1,55 @@+# CD4011S++**GR** · Gates · SOP-14++CD4011S from GR, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | A1 | input | Input A of NAND gate 1. CMOS logic input; VIH>=3.5V @ VDD=5V, VIL<=1.5V @ VDD=5V. Input current <= 1uA. |+| 2 | B1 | input | Input B of NAND gate 1. CMOS logic input paired with A1. |+| 3 | Y1 | output | Output of NAND gate 1: Y1 = NAND(A1, B1). VOH >= 4.95V @ VDD=5V (|IOUT|<1uA); typical sourcing -1.0mA @ Vo=4.6V, sinking 2.2mA @ Vo=0.4V. |+| 4 | Y2 | output | Output of NAND gate 2: Y2 = NAND(A2, B2). Same drive characteristics as Y1. |+| 5 | A2 | input | Input A of NAND gate 2. CMOS logic input. |+| 6 | B2 | input | Input B of NAND gate 2. CMOS logic input paired with A2. |+| 7 | VSS | power_in | Negative supply / ground reference (0V). Absolute maximum VDD-VSS = 18V. |+| 8 | A3 | input | Input A of NAND gate 3. CMOS logic input. |+| 9 | B3 | input | Input B of NAND gate 3. CMOS logic input paired with A3. |+| 10 | Y3 | output | Output of NAND gate 3: Y3 = NAND(A3, B3). |+| 11 | Y4 | output | Output of NAND gate 4: Y4 = NAND(A4, B4). |+| 12 | A4 | input | Input A of NAND gate 4. CMOS logic input. |+| 13 | B4 | input | Input B of NAND gate 4. CMOS logic input paired with A4. |+| 14 | VDD | power_in | Positive supply. Recommended 2.5V to 15V; absolute maximum -0.5V to +18V referenced to VSS. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | GR |+| Package | SOP-14 |+| Category | Logic |+| Pins | 14 |++## Ordering variants++- `CD4011SS`+- `CD4011SD`++## CAD (KiCad official)++- Symbol: `CD4011S`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOP-14 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [GR datasheet](docs/cd4011s-datasheet.pdf) (5 pp, sha256 `c6ad9d7e0313c497`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4011s-datasheet.pdf)
page.jsonadded+34@@ -0,0 +1,34 @@+{+ "slug": "cd4011s",+ "version": "0.1.0",+ "type": "component",+ "description": "GR Gates, SOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "cd4011s"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cd4011s.kicad_sym",+ "cd4011s.kicad_mod",+ "cd4011s.glb",+ "cd4011s.step",+ "cd4011s.lbr",+ "docs/hero.png",+ "docs/cd4011s-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "visibility": "public",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}