component
CD4011BM
Public Made by Adomby adom
HGSEMI Gates, SOIC-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+152−8@@ -1,13 +1,162 @@ {+ "schema_version": 1,+ "type": "component", "slug": "cd4011bm",+ "title": "CD4011BM",+ "brief": "HGSEMI Gates, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "HGSEMI Gates, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic", "cd4011bm" ],+ "component": {+ "mpn": "CD4011BM",+ "manufacturer": "HGSEMI",+ "package": "SOIC-14",+ "pin_count": 14,+ "category": "Logic",+ "subcategory": "Gates",+ "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/933061181c86fce802b32c457002f266.pdf",+ "parts": {+ "symbol": "cd4011bm.kicad_sym",+ "footprint": "cd4011bm.kicad_mod",+ "model_3d": "cd4011bm.glb",+ "model_3d_step": "cd4011bm.step",+ "lbr": "cd4011bm.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "I1",+ "type": "input",+ "description": "Gate 1 input A. CMOS logic input; VIL max 1.5 V @ VDD=5 V, VIH min 3.5 V @ VDD=5 V. Input leakage <=0.3 uA typ at VDD=15 V."+ },+ {+ "number": "2",+ "name": "I2",+ "type": "input",+ "description": "Gate 1 input B. CMOS logic input paired with I1; NANDed to produce O1."+ },+ {+ "number": "3",+ "name": "O1",+ "type": "output",+ "description": "Gate 1 buffered NAND output = NAND(I1, I2). VOH >= VDD-0.05 V, VOL <= 0.05 V at |Io| < 1 uA. Sinks/sources 0.44 mA at VDD=5 V (typ)."+ },+ {+ "number": "4",+ "name": "O2",+ "type": "output",+ "description": "Gate 2 buffered NAND output = NAND(I3, I4). Buffered CMOS output."+ },+ {+ "number": "5",+ "name": "I3",+ "type": "input",+ "description": "Gate 2 input A. CMOS logic input."+ },+ {+ "number": "6",+ "name": "I4",+ "type": "input",+ "description": "Gate 2 input B. CMOS logic input paired with I3."+ },+ {+ "number": "7",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground / negative supply reference (0 V). All input logic levels referenced to VSS."+ },+ {+ "number": "8",+ "name": "I5",+ "type": "input",+ "description": "Gate 3 input A. CMOS logic input."+ },+ {+ "number": "9",+ "name": "I6",+ "type": "input",+ "description": "Gate 3 input B. CMOS logic input paired with I5."+ },+ {+ "number": "10",+ "name": "O3",+ "type": "output",+ "description": "Gate 3 buffered NAND output = NAND(I5, I6)."+ },+ {+ "number": "11",+ "name": "O4",+ "type": "output",+ "description": "Gate 4 buffered NAND output = NAND(I7, I8)."+ },+ {+ "number": "12",+ "name": "I7",+ "type": "input",+ "description": "Gate 4 input A. CMOS logic input."+ },+ {+ "number": "13",+ "name": "I8",+ "type": "input",+ "description": "Gate 4 input B. CMOS logic input paired with I7."+ },+ {+ "number": "14",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply. Recommended VDD = 3 V to 15 V; absolute max -0.5 V to +18 V. Quiescent current IDD <= 7.5 uA at VDD=5 V (25 degC)."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://datasheet.lcsc.com/datasheet/pdf/933061181c86fce802b32c457002f266.pdf",+ "pages": 10,+ "sha256": "5f5ccfab60c3ae62",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "HGSEMI",+ "Package": "SOIC-14",+ "Category": "Logic",+ "Pins": "14"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "cd4011bm"+ ],+ "discovery_pitch": "CD4011BM (HGSEMI) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +174,5 @@ "docs/cd4011bm-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }