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cd40109bpwr: factory component page (tier=mfr)

Ray ·1dc99f7642 · ·parent 297cf09
1 file changed +164−8
page.json+164−8
@@ -1,13 +1,174 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "cd40109bpwr",+  "title": "CD40109BPWR",+  "brief": "Texas Instruments Translators / Level Shifters, TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",-  "type": "component",-  "description": "Texas Instruments Translators / Level Shifters, TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "logic",     "cd40109bpwr"   ],+  "component": {+    "mpn": "CD40109BPWR",+    "manufacturer": "Texas Instruments",+    "package": "TSSOP-16",+    "pin_count": 16,+    "category": "Logic",+    "subcategory": "Translators / Level Shifters",+    "datasheet": "https://www.ti.com/lit/ds/symlink/cd40109b.pdf",+    "parts": {+      "symbol": "cd40109bpwr.kicad_sym",+      "footprint": "cd40109bpwr.kicad_mod",+      "model_3d": "cd40109bpwr.glb",+      "model_3d_step": "cd40109bpwr.step",+      "lbr": "cd40109bpwr.lbr"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "VCC",+        "type": "power_in",+        "description": "Low-voltage supply for the input logic side. Recommended 3-18V; must be \u2264 VDD in normal use (mode VCC > VDD is allowed for high-to-low shifting)."+      },+      {+        "number": "2",+        "name": "ENABLE A",+        "type": "input",+        "description": "Three-state enable for channel A\u2192E output. Logic 1 (=VCC) enables the output; logic 0 (=VSS) places output E in high-impedance state."+      },+      {+        "number": "3",+        "name": "A",+        "type": "input",+        "description": "Low-voltage logic data input for channel A. Logic 1 = VCC, logic 0 = VSS; shifted to output E at VDD levels."+      },+      {+        "number": "4",+        "name": "E",+        "type": "tri_state",+        "description": "High-voltage three-state logic output for channel A\u2192E. Logic 1 = VDD, logic 0 = VSS; high-Z when ENABLE A = 0."+      },+      {+        "number": "5",+        "name": "F",+        "type": "tri_state",+        "description": "High-voltage three-state logic output for channel B\u2192F. Logic 1 = VDD, logic 0 = VSS; high-Z when ENABLE B = 0."+      },+      {+        "number": "6",+        "name": "B",+        "type": "input",+        "description": "Low-voltage logic data input for channel B. Logic 1 = VCC, logic 0 = VSS; shifted to output F at VDD levels."+      },+      {+        "number": "7",+        "name": "ENABLE B",+        "type": "input",+        "description": "Three-state enable for channel B\u2192F output. Logic 1 = VCC enables the output; logic 0 places output F in high-impedance state."+      },+      {+        "number": "8",+        "name": "VSS",+        "type": "power_in",+        "description": "Ground / negative supply, common to both VCC and VDD rails."+      },+      {+        "number": "9",+        "name": "ENABLE C",+        "type": "input",+        "description": "Three-state enable for channel C\u2192G output. Logic 1 = VCC enables the output; logic 0 places output G in high-impedance state."+      },+      {+        "number": "10",+        "name": "C",+        "type": "input",+        "description": "Low-voltage logic data input for channel C. Logic 1 = VCC, logic 0 = VSS; shifted to output G at VDD levels."+      },+      {+        "number": "11",+        "name": "G",+        "type": "tri_state",+        "description": "High-voltage three-state logic output for channel C\u2192G. Logic 1 = VDD, logic 0 = VSS; high-Z when ENABLE C = 0."+      },+      {+        "number": "12",+        "name": "NC",+        "type": "unconnected",+        "description": "No internal connection. Leave floating or tie as convenient for PCB routing."+      },+      {+        "number": "13",+        "name": "H",+        "type": "tri_state",+        "description": "High-voltage three-state logic output for channel D\u2192H. Logic 1 = VDD, logic 0 = VSS; high-Z when ENABLE D = 0."+      },+      {+        "number": "14",+        "name": "D",+        "type": "input",+        "description": "Low-voltage logic data input for channel D. Logic 1 = VCC, logic 0 = VSS; shifted to output H at VDD levels."+      },+      {+        "number": "15",+        "name": "ENABLE D",+        "type": "input",+        "description": "Three-state enable for channel D\u2192H output. Logic 1 = VCC enables the output; logic 0 places output H in high-impedance state."+      },+      {+        "number": "16",+        "name": "VDD",+        "type": "power_in",+        "description": "High-voltage supply for the output side. Recommended 3-18V; sets the output logic-1 level. Absolute max 20V referenced to VSS."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://www.ti.com/lit/ds/symlink/cd40109b.pdf",+        "pages": 18,+        "sha256": "945f61ad7c94f1e9",+        "source_tier": "mfr"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 16,+        "described": 16,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Manufacturer": "Texas Instruments",+      "Package": "TSSOP-16",+      "Category": "Logic",+      "Pins": "16"+    }+  },+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "cd40109bpwr"+  ],+  "discovery_pitch": "CD40109BPWR (Texas Instruments) component page with datasheet-verified CAD.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -25,10 +186,5 @@     "docs/cd40109bpwr-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file