component
CAT25512VI-GT3
Public Made by Adomby adom
onsemi EEPROM, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
page.json+116−8@@ -1,13 +1,126 @@ {+ "schema_version": 1,+ "type": "component", "slug": "cat25512vi-gt3",+ "title": "CAT25512VI-GT3",+ "brief": "onsemi EEPROM, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "onsemi EEPROM, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "memory", "cat25512vi-gt3" ],+ "component": {+ "mpn": "CAT25512VI-GT3",+ "manufacturer": "onsemi",+ "package": "SOIC-8",+ "pin_count": 8,+ "category": "Memory",+ "subcategory": "EEPROM",+ "datasheet": "https://www.onsemi.com/pdf/datasheet/cat25512vi-gt3-d.pdf",+ "parts": {+ "symbol": "cat25512vi-gt3.kicad_sym",+ "footprint": "cat25512vi-gt3.kicad_mod",+ "model_3d": "cat25512vi-gt3.glb",+ "model_3d_step": "cat25512vi-gt3.step",+ "lbr": "cat25512vi-gt3.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "CS",+ "type": "input",+ "description": "Active-low chip select. Every SPI transaction must begin with a HIGH-to-LOW transition on CS and end with a LOW-to-HIGH transition. When CS is HIGH the device is in Standby Mode and SO is tri-stated."+ },+ {+ "number": "2",+ "name": "SO",+ "type": "output",+ "description": "Serial data output. Data is shifted out on the falling edge of SCK in SPI modes (0,0) and (1,1). Output is high-impedance when CS is HIGH or HOLD is asserted low."+ },+ {+ "number": "3",+ "name": "WP",+ "type": "input",+ "description": "Active-low write protect. When WP is held low and the WPEN bit in the Status Register is 1, writing to the Status Register is disabled (hardware write protection)."+ },+ {+ "number": "4",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference for supply and I/O."+ },+ {+ "number": "5",+ "name": "SI",+ "type": "input",+ "description": "Serial data input. Accepts op-codes, addresses, and write data. Data is latched on the rising edge of SCK in SPI modes (0,0) and (1,1)."+ },+ {+ "number": "6",+ "name": "SCK",+ "type": "input",+ "description": "Serial clock input, provided by the SPI host to synchronize communication. Supports DC to 20 MHz depending on VCC."+ },+ {+ "number": "7",+ "name": "HOLD",+ "type": "input",+ "description": "Active-low hold input used to pause an SPI transmission without dropping CS. Taking HOLD low freezes the interface; taking it high resumes with SCK low during both transitions. Tie to VCC (directly or via a pull-up) when not used."+ },+ {+ "number": "8",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply, 1.8 V to 5.5 V. Read supply current up to 3 mA at 20 MHz; write supply current up to 2 mA. Standby current typically <5 uA."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://www.onsemi.com/pdf/datasheet/cat25512vi-gt3-d.pdf",+ "pages": 17,+ "sha256": "ff68b0f40b13b7de",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 8,+ "described": 8,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "onsemi",+ "Package": "SOIC-8",+ "Category": "Memory",+ "Pins": "8"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "cat25512vi-gt3"+ ],+ "discovery_pitch": "CAT25512VI-GT3 (onsemi) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +138,5 @@ "docs/cat25512vi-gt3-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }