cat25160vi-gt3

@@ -33,5 +33,78 @@   "author": {     "name": "Ray",     "email": "[email protected]"+  },+  "component": {+    "mpn": "CAT25160VI-GT3",+    "manufacturer": "onsemi",+    "package": "SOIC-8",+    "pin_count": 8,+    "category": "EEPROM",+    "parts": {+      "symbol": "cat25160vi-gt3.kicad_sym",+      "footprint": "cat25160vi-gt3.kicad_mod",+      "model_3d": "cat25160vi-gt3-etched.glb",+      "model_3d_plain": "cat25160vi-gt3.glb",+      "model_3d_step": "cat25160vi-gt3-etched.step",+      "model_3d_step_plain": "cat25160vi-gt3.step",+      "lbr": "cat25160vi-gt3.lbr"+    },+    "pins": [+      {+        "number": "1",+        "name": "CS",+        "type": "input",+        "description": "Active-low chip select. Every SPI transaction must begin with a high-to-low transition and end with a low-to-high transition on CS. When CS is high, SO is tri-stated and the device enters standby mode (unless an internal write is in progress). VIL = -0.5 V to 0.3*VCC, VIH = 0.7*VCC to VCC+0.5 V."+      },+      {+        "number": "2",+        "name": "SO",+        "type": "output",+        "description": "Serial data output. Data is shifted out on the falling edge of SCK in SPI modes (0,0) and (1,1). High-impedance when CS is high or during a HOLD condition. Drives VOL = 0.4 V @ 3 mA (VCC>2.5 V) and VOH = VCC-0.8 V @ -1.6 mA."+      },+      {+        "number": "3",+        "name": "WP",+        "type": "input",+        "description": "Active-low write protect. When WP is held low and the WPEN bit in the Status Register is set to '1', writes to the Status Register are disabled, providing hardware write protection. Tie high to allow normal write operations."+      },+      {+        "number": "4",+        "name": "VSS",+        "type": "power_in",+        "description": "Ground reference for the device (0 V)."+      },+      {+        "number": "5",+        "name": "SI",+        "type": "input",+        "description": "Serial data input. Accepts op-codes, addresses, and data. Data is latched on the rising edge of SCK in SPI modes (0,0) and (1,1)."+      },+      {+        "number": "6",+        "name": "SCK",+        "type": "input",+        "description": "Serial clock input from the SPI host. Synchronizes data transfer on SI and SO. Supports DC to 20 MHz operation at VCC = 4.5-5.5 V (10 MHz at 2.5-5.5 V, 5 MHz at 1.8-5.5 V)."+      },+      {+        "number": "7",+        "name": "HOLD",+        "type": "input",+        "description": "Active-low hold input used to pause SPI communication without retransmitting the sequence. To pause, drive HOLD low while SCK is low; to resume, drive HOLD high while SCK is low. When not used, tie to VCC directly or via a pull-up resistor."+      },+      {+        "number": "8",+        "name": "VCC",+        "type": "power_in",+        "description": "Positive supply, 1.8 V to 5.5 V. Typical supply current is 2 mA during read/write at 10 MHz; standby current is ~2 uA (WP=VCC) or 4-5 uA (WP=GND)."+      }+    ],+    "provenance": {+      "rebuilt": "component block rebuilt 2026-10-05 from this page's own README pinout table and .kicad_sym (pins cross-checked), no re-extraction"+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }   }-}\ No newline at end of file+}