cat25128vi-gt3

@@ -33,5 +33,79 @@   "author": {     "name": "Ray",     "email": "[email protected]"+  },+  "component": {+    "mpn": "CAT25128VI-GT3",+    "manufacturer": "onsemi",+    "package": "SOIC-8",+    "pin_count": 8,+    "category": "EEPROM",+    "datasheet": "https://www.onsemi.com/pdf/datasheet/cat25128vi-gt3-d.pdf",+    "parts": {+      "symbol": "cat25128vi-gt3.kicad_sym",+      "footprint": "cat25128vi-gt3.kicad_mod",+      "model_3d": "cat25128vi-gt3-etched.glb",+      "model_3d_plain": "cat25128vi-gt3.glb",+      "model_3d_step": "cat25128vi-gt3-etched.step",+      "model_3d_step_plain": "cat25128vi-gt3.step",+      "lbr": "cat25128vi-gt3.lbr"+    },+    "pins": [+      {+        "number": "1",+        "name": "CS",+        "type": "input",+        "description": "Active-low chip select. Enables the device on a high-to-low transition and returns SO to Hi-Z / puts the device in standby when high. Every SPI transaction must be framed by a falling and rising edge of CS."+      },+      {+        "number": "2",+        "name": "SO",+        "type": "tri_state",+        "description": "Serial data output. In SPI modes (0,0) and (1,1) data is shifted out on the falling edge of SCK. Tri-stated (Hi-Z) when CS is high or HOLD is low."+      },+      {+        "number": "3",+        "name": "WP",+        "type": "input",+        "description": "Active-low hardware write protect. When WP is low and the Status Register WPEN bit = 1, writes to the Status Register are inhibited. When WPEN = 0 or WP is high, the pin has no effect."+      },+      {+        "number": "4",+        "name": "VSS",+        "type": "power_in",+        "description": "Device ground reference. Connect to system ground."+      },+      {+        "number": "5",+        "name": "SI",+        "type": "input",+        "description": "Serial data input. Accepts op-codes, address and data. In SPI modes (0,0) and (1,1) input data is latched on the rising edge of SCK."+      },+      {+        "number": "6",+        "name": "SCK",+        "type": "input",+        "description": "Serial clock input. Provided by the SPI host to synchronize communication with the CAT25128. Supports DC to 20 MHz operation at VCC = 4.5-5.5 V."+      },+      {+        "number": "7",+        "name": "HOLD",+        "type": "input",+        "description": "Active-low hold input. Pauses SPI communication when driven low while SCK is low (SO goes Hi-Z, SI is ignored); resumes when driven high while SCK is low. When unused, tie to VCC directly or through a resistor."+      },+      {+        "number": "8",+        "name": "VCC",+        "type": "power_in",+        "description": "Positive supply input. Operating range 1.8 V to 5.5 V. Recommended local bypass to VSS."+      }+    ],+    "provenance": {+      "rebuilt": "component block rebuilt 2026-10-05 from this page's own README pinout table and .kicad_sym (pins cross-checked), no re-extraction"+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }   }-}\ No newline at end of file+}