component
cat25128vi-gt3
Public Made by Adomby adom
onsemi EEPROM, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.
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README.mdadded+60@@ -0,0 +1,60 @@+# CAT25128VI-GT3++**onsemi** · EEPROM · SOIC-8++CAT25128VI-GT3 from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CS | input | Active-low chip select. Enables the device on a high-to-low transition and returns SO to Hi-Z / puts the device in standby when high. Every SPI transaction must be framed by a falling and rising edge of CS. |+| 2 | SO | tri_state | Serial data output. In SPI modes (0,0) and (1,1) data is shifted out on the falling edge of SCK. Tri-stated (Hi-Z) when CS is high or HOLD is low. |+| 3 | WP | input | Active-low hardware write protect. When WP is low and the Status Register WPEN bit = 1, writes to the Status Register are inhibited. When WPEN = 0 or WP is high, the pin has no effect. |+| 4 | VSS | power_in | Device ground reference. Connect to system ground. |+| 5 | SI | input | Serial data input. Accepts op-codes, address and data. In SPI modes (0,0) and (1,1) input data is latched on the rising edge of SCK. |+| 6 | SCK | input | Serial clock input. Provided by the SPI host to synchronize communication with the CAT25128. Supports DC to 20 MHz operation at VCC = 4.5-5.5 V. |+| 7 | HOLD | input | Active-low hold input. Pauses SPI communication when driven low while SCK is low (SO goes Hi-Z, SI is ignored); resumes when driven high while SCK is low. When unused, tie to VCC directly or through a resistor. |+| 8 | VCC | power_in | Positive supply input. Operating range 1.8 V to 5.5 V. Recommended local bypass to VSS. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | onsemi |+| Package | SOIC-8 |+| Category | Memory |+| Pins | 8 |++## Ordering variants++- `CAT25128VI-GT3`+- `CAT25128VI-GT3VE-G`+- `CAT25128VI-GT3VE-GT3`+- `CAT25128VI-GT3XI-T2`+- `CAT25128VI-GT3XE-T2`+- `CAT25128VI-GT3LI-G`+- `CAT25128VI-GT3YI-G`+- `CAT25128VI-GT3YI-GT3`+- `CAT25128VI-GT3YE-G`+- `CAT25128VI-GT3YE-GT3`+- `CAT25128VI-GT3VP2I-GT3`+- `CAT25128VI-GT3VP2E-GT3`+- `CAT25128VI-GT3HU4I-GT3`+- `CAT25128VI-GT3HU4E-GT3`++## CAD (KiCad official)++- Symbol: `CAT25128VI-GT3`+- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`+- 3D model: SOIC-8 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/cat25128vi-gt3-d.pdf) (None pp, sha256 `6757827cecd36277`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cat25128vi-gt3-datasheet.pdf)
page.jsonadded+34@@ -0,0 +1,34 @@+{+ "slug": "cat25128vi-gt3",+ "version": "0.1.0",+ "type": "component",+ "description": "onsemi EEPROM, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "memory",+ "cat25128vi-gt3"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cat25128vi-gt3.kicad_sym",+ "cat25128vi-gt3.kicad_mod",+ "cat25128vi-gt3.glb",+ "cat25128vi-gt3.step",+ "cat25128vi-gt3.lbr",+ "docs/hero.png",+ "docs/cat25128vi-gt3-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "visibility": "public",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}