ca-is3720hg

@@ -33,5 +33,78 @@   "author": {     "name": "Ray",     "email": "[email protected]"+  },+  "component": {+    "mpn": "CA-IS3720HG",+    "manufacturer": "Chipanalog",+    "package": "SOIC-8-300mil",+    "pin_count": 8,+    "category": "Digital Isolators",+    "parts": {+      "symbol": "ca-is3720hg.kicad_sym",+      "footprint": "ca-is3720hg.kicad_mod",+      "model_3d": "ca-is3720hg-etched.glb",+      "model_3d_plain": "ca-is3720hg.glb",+      "model_3d_step": "ca-is3720hg-etched.step",+      "model_3d_step_plain": "ca-is3720hg.step",+      "lbr": "ca-is3720hg.lbr"+    },+    "pins": [+      {+        "number": "1",+        "name": "VDDA",+        "type": "power_in",+        "description": "A-side supply voltage. Operating range 2.375 V to 5.5 V (typ 3.3 V/5 V). Decouple to GNDA with a low-ESR ceramic capacitor placed close to the pin."+      },+      {+        "number": "2",+        "name": "VI1",+        "type": "input",+        "description": "A-side logic input for channel 1. Schmitt-trigger CMOS input (VIT+ typ 1.67 V, VIT- typ 1.23 V, hysteresis typ 0.44 V). Signal is transmitted across the isolation barrier to VO1 on the B side."+      },+      {+        "number": "3",+        "name": "VI2",+        "type": "input",+        "description": "A-side logic input for channel 2. Schmitt-trigger CMOS input (same thresholds as VI1). Signal is transmitted across the isolation barrier to VO2 on the B side."+      },+      {+        "number": "4",+        "name": "GNDA",+        "type": "power_in",+        "description": "A-side ground reference. All A-side voltages (VDDA, VI1, VI2) are referenced to this pin. Isolated from GNDB by the internal SiO2 barrier."+      },+      {+        "number": "5",+        "name": "GNDB",+        "type": "power_in",+        "description": "B-side ground reference. All B-side voltages (VDDB, VO1, VO2) are referenced to this pin. Isolated from GNDA by the internal SiO2 barrier."+      },+      {+        "number": "6",+        "name": "VO2",+        "type": "output",+        "description": "B-side logic output for channel 2. Reconstructed CMOS copy of VI2. Drives VDDO−0.4 V high / 0.4 V low at ±4 mA (5 V supply). Output impedance ~50 Ω. Defaults HIGH on loss of input power or signal (H-suffix fail-safe)."+      },+      {+        "number": "7",+        "name": "VO1",+        "type": "output",+        "description": "B-side logic output for channel 1. Reconstructed CMOS copy of VI1. Drives VDDO−0.4 V high / 0.4 V low at ±4 mA (5 V supply). Output impedance ~50 Ω. Defaults HIGH on loss of input power or signal (H-suffix fail-safe)."+      },+      {+        "number": "8",+        "name": "VDDB",+        "type": "power_in",+        "description": "B-side supply voltage. Operating range 2.375 V to 5.5 V; sets the CMOS output swing on VO1/VO2. Decouple to GNDB with a low-ESR ceramic capacitor placed close to the pin."+      }+    ],+    "provenance": {+      "rebuilt": "component block rebuilt 2026-10-05 from this page's own README pinout table and .kicad_sym (pins cross-checked), no re-extraction"+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }   }-}\ No newline at end of file+}