CA-IS3644HVW

@@ -0,0 +1,61 @@+# CA-IS3644HVW++**Chipanalog** · Digital Isolators (With Power) · SOIC-16++CA-IS3644HVW from Chipanalog, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VDD | power_in | A-side power supply for the internal DC-DC converter primary (3.15 V to 5.5 V). Bypass to GNDA with 0.1 uF and 10 uF placed within 2 mm of the pin. |+| 2 | GNDA | power_in | A-side ground reference. |+| 3 | VO1 | output | Channel 1 A-side logic output (receives data from B-side input VI1 on pin 14). Output level is set by VDDL. Default state HIGH on failure per the H suffix. |+| 4 | VO2 | output | Channel 2 A-side logic output (receives data from B-side input VI2 on pin 13). Output level is set by VDDL. Default state HIGH on failure. |+| 5 | VO3 | output | Channel 3 A-side logic output (receives data from B-side input VI3 on pin 12). Output level is set by VDDL. Default state HIGH on failure. |+| 6 | VO4 | output | Channel 4 A-side logic output (receives data from B-side input VI4 on pin 11). Output level is set by VDDL. Default state HIGH on failure. |+| 7 | VDDL | power_in | A-side logic supply (2.375 V to 5.5 V). Sets the A-side input logic threshold and A-side output HIGH level. Present because this part is the 'V' variant (CA-IS3644HVW); on the non-V CA-IS3644HW this pin is NC. |+| 8 | GNDA | power_in | A-side ground reference (second GNDA pin). |+| 9 | GNDB | power_in | B-side (isolated) ground reference. |+| 10 | SEL | input | VISO output-voltage select. Tie to VISO for VISO = 5 V; tie to GNDB or leave floating for VISO = 3.3 V. Referenced to the B-side domain. |+| 11 | VI4 | input | Channel 4 B-side logic input; drives the A-side output VO4 on pin 6. Input threshold referenced to VISO (B-side domain). |+| 12 | VI3 | input | Channel 3 B-side logic input; drives the A-side output VO3 on pin 5. |+| 13 | VI2 | input | Channel 2 B-side logic input; drives the A-side output VO2 on pin 4. |+| 14 | VI1 | input | Channel 1 B-side logic input; drives the A-side output VO1 on pin 3. |+| 15 | GNDB | power_in | B-side (isolated) ground reference (second GNDB pin). |+| 16 | VISO | power_out | Isolated B-side output voltage generated by the internal DC-DC converter. 3.3 V or 5 V selected by the SEL pin. Bypass to GNDB with 0.1 uF and 10 uF placed within 2 mm of the pin. Supplies up to ~120 mA (5V/1Mbps) or ~80 mA at 100 Mbps depending on channel loading. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Chipanalog |+| Package | SOIC-16 |+| Category | Signal Isolation Devices |+| Pins | 16 |++## Ordering variants++Same part, different packaging or reel option.++- `CA-IS3644HVW`+- `CA-IS3644HVWLVW`+- `CA-IS3644HVWHW`+- `CA-IS3644HVWLW`++## CAD (KiCad official)++- Symbol: `CA-IS3644HVW`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Chipanalog datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590235090224910336) (39 pp, sha256 `74e1e848c9ed7ac2`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ca-is3644hvw-datasheet.pdf)

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