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CA-IS3082CWX
Public Made by Adomby adom
Chipanalog Isolated RS-485/422 Transceivers, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+53@@ -0,0 +1,53 @@+# CA-IS3082CWX++**Chipanalog** · Isolated RS-485/422 Transceivers · SOIC-16-300mil++CA-IS3082CWX from Chipanalog, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VDDA | power_in | Logic side power supply input; connect 0.1μF and 1μF bypass capacitors between VDDA and GNDA pins as close as possible to device pins. |+| 2 | GNDA | power_in | Logic side ground, providing ground reference for digital signals. |+| 3 | RO | output | Receiver data output; when RE is low (receiver enabled), outputs high if (VA - VB) ≥ -50mV or low if (VA - VB) ≤ -200mV; outputs high impedance when RE is high. |+| 4 | RE | input | Receiver enable control input with internal weak pull-up; low level enables receiver, high level disables receiver output. |+| 5 | DE | input | Driver enable control input with internal weak pull-down, high level active; low level inhibits data transmission and sets driver output to high impedance. |+| 6 | DI | input | Driver data input with internal weak pull-up; when DE is high, high level on DI produces high on A and low on B; low level produces opposite result. |+| 7 | GNDA | power_in | Logic side ground, providing ground reference for digital signals. |+| 8 | GNDA | power_in | Logic side ground, providing ground reference for digital signals. |+| 9 | GNDB | power_in | Bus side ground, providing ground reference for RS-485 bus signals. |+| 10 | GNDB | power_in | Bus side ground, providing ground reference for RS-485 bus signals. |+| 11 | NC | unconnected | No internal connection; can be connected to VDDB, GNDB, or left floating. |+| 12 | A | bidirectional | RS-485 bus in-phase output from driver / in-phase input to receiver; differential pair with pin 13; operates as driver output when DE=high, receiver input when RE=low. |+| 13 | B | bidirectional | RS-485 bus anti-phase output from driver / anti-phase input to receiver; differential pair with pin 12; operates as driver output when DE=high, receiver input when RE=low. |+| 14 | NC | unconnected | No internal connection; can be connected to VDDB, GNDB, or left floating. |+| 15 | GNDB | power_in | Bus side ground, providing ground reference for RS-485 bus signals. |+| 16 | VDDB | power_in | Bus side power supply input; connect 0.1μF and 1μF bypass capacitors between VDDB and GNDB pins as close as possible to device pins. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Chipanalog |+| Package | SOIC-16-300mil |+| Category | Signal Isolation Devices |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CA-IS3082CWX`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16-300mil (KiCad packages3D, STEP)+- 3D model files: `ca-is3082cwx-etched.step` / `ca-is3082cwx-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ca-is3082cwx.step` / `ca-is3082cwx.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Chipanalog datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8604439403339132928) (22 pp, sha256 `9eab96b1cb24d97f`, retrieved 2026-09-21, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ca-is3082cwx-datasheet.pdf)
page.jsonadded+189@@ -0,0 +1,189 @@+{+ "slug": "ca-is3082cwx",+ "version": "0.1.0",+ "type": "component",+ "description": "Chipanalog Isolated RS-485/422 Transceivers, SOIC-16-300mil. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "signal isolation devices",+ "ca-is3082cwx",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "ca-is3082cwx.kicad_sym",+ "ca-is3082cwx.kicad_mod",+ "ca-is3082cwx.glb",+ "ca-is3082cwx.step",+ "ca-is3082cwx.lbr",+ "docs/hero.png",+ "docs/ca-is3082cwx-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "CA-IS3082CWX",+ "manufacturer": "Chipanalog",+ "package": "SOIC-16-300mil",+ "pin_count": 16,+ "category": "Signal Isolation Devices",+ "subcategory": "Isolated RS-485/422 Transceivers",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8604439403339132928",+ "parts": {+ "symbol": "ca-is3082cwx.kicad_sym",+ "footprint": "ca-is3082cwx.kicad_mod",+ "model_3d": "ca-is3082cwx-etched.glb",+ "model_3d_plain": "ca-is3082cwx.glb",+ "model_3d_step": "ca-is3082cwx-etched.step",+ "model_3d_step_plain": "ca-is3082cwx.step",+ "lbr": "ca-is3082cwx.lbr"+ },+ "distributor_links": {+ "lcsc": "C41784141"+ },+ "pins": [+ {+ "number": "1",+ "name": "VDDA",+ "type": "power_in",+ "description": "Logic side power supply input; connect 0.1μF and 1μF bypass capacitors between VDDA and GNDA pins as close as possible to device pins."+ },+ {+ "number": "2",+ "name": "GNDA",+ "type": "power_in",+ "description": "Logic side ground, providing ground reference for digital signals."+ },+ {+ "number": "3",+ "name": "RO",+ "type": "output",+ "description": "Receiver data output; when RE is low (receiver enabled), outputs high if (VA - VB) ≥ -50mV or low if (VA - VB) ≤ -200mV; outputs high impedance when RE is high."+ },+ {+ "number": "4",+ "name": "RE",+ "type": "input",+ "description": "Receiver enable control input with internal weak pull-up; low level enables receiver, high level disables receiver output."+ },+ {+ "number": "5",+ "name": "DE",+ "type": "input",+ "description": "Driver enable control input with internal weak pull-down, high level active; low level inhibits data transmission and sets driver output to high impedance."+ },+ {+ "number": "6",+ "name": "DI",+ "type": "input",+ "description": "Driver data input with internal weak pull-up; when DE is high, high level on DI produces high on A and low on B; low level produces opposite result."+ },+ {+ "number": "7",+ "name": "GNDA",+ "type": "power_in",+ "description": "Logic side ground, providing ground reference for digital signals."+ },+ {+ "number": "8",+ "name": "GNDA",+ "type": "power_in",+ "description": "Logic side ground, providing ground reference for digital signals."+ },+ {+ "number": "9",+ "name": "GNDB",+ "type": "power_in",+ "description": "Bus side ground, providing ground reference for RS-485 bus signals."+ },+ {+ "number": "10",+ "name": "GNDB",+ "type": "power_in",+ "description": "Bus side ground, providing ground reference for RS-485 bus signals."+ },+ {+ "number": "11",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection; can be connected to VDDB, GNDB, or left floating."+ },+ {+ "number": "12",+ "name": "A",+ "type": "bidirectional",+ "description": "RS-485 bus in-phase output from driver / in-phase input to receiver; differential pair with pin 13; operates as driver output when DE=high, receiver input when RE=low."+ },+ {+ "number": "13",+ "name": "B",+ "type": "bidirectional",+ "description": "RS-485 bus anti-phase output from driver / anti-phase input to receiver; differential pair with pin 12; operates as driver output when DE=high, receiver input when RE=low."+ },+ {+ "number": "14",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection; can be connected to VDDB, GNDB, or left floating."+ },+ {+ "number": "15",+ "name": "GNDB",+ "type": "power_in",+ "description": "Bus side ground, providing ground reference for RS-485 bus signals."+ },+ {+ "number": "16",+ "name": "VDDB",+ "type": "power_in",+ "description": "Bus side power supply input; connect 0.1μF and 1μF bypass capacitors between VDDB and GNDB pins as close as possible to device pins."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 22,+ "cost_usd": 0.2182,+ "at": "2026-09-21T16:17:07"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8604439403339132928",+ "pages": 22,+ "sha256": "9eab96b1cb24d97f",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}