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CA-IS3021W
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Chipanalog I2C Isolators, SOIC-16-300mil. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+60@@ -0,0 +1,60 @@+# CA-IS3021W++**Chipanalog** · I2C Isolators · SOIC-16-300mil++CA-IS3021W from Chipanalog, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GNDA | power_in | Side A ground reference. |+| 2 | NC | unconnected | No internal connection. Leave floating (do not connect externally). |+| 3 | VDDA | power_in | Side A supply input, 3.0 V to 5.5 V. Bypass to GNDA with a local decoupling capacitor. |+| 4 | NC | unconnected | No internal connection. Leave floating (do not connect externally). |+| 5 | SDAA | bidirectional | Side A bidirectional I2C data (open-drain). Mirrors SDAB across the isolation barrier; requires external pull-up to VDDA. |+| 6 | SCLA | input | Side A I2C clock input. Drives the unidirectional SCL channel that appears at SCLB on side B. |+| 7 | GNDA | power_in | Side A ground reference (redundant pin, tie to pin 1). |+| 8 | NC | unconnected | No internal connection. Leave floating (do not connect externally). |+| 9 | GNDB | power_in | Side B ground reference. |+| 10 | NC | unconnected | No internal connection. Leave floating (do not connect externally). |+| 11 | SCLB | output | Side B I2C clock output (open-drain), driven from SCLA on side A. Requires external pull-up to VDDB. |+| 12 | SDAB | bidirectional | Side B bidirectional I2C data (open-drain). Mirrors SDAA across the isolation barrier; requires external pull-up to VDDB. |+| 13 | NC | unconnected | No internal connection. Leave floating (do not connect externally). |+| 14 | VDDB | power_in | Side B supply input, 3.0 V to 5.5 V. Bypass to GNDB with a local decoupling capacitor. |+| 15 | NC | unconnected | No internal connection. Leave floating (do not connect externally). |+| 16 | GNDB | power_in | Side B ground reference (redundant pin, tie to pin 9). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Chipanalog |+| Package | SOIC-16-300mil |+| Category | Signal Isolation Devices |+| Pins | 16 |++## Ordering variants++Same part, different packaging or reel option.++- `CA-IS3021WW`+- `CA-IS3021WG`+- `CA-IS3021WS`++## CAD (KiCad official)++- Symbol: `CA-IS3021W`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16-300mil (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Chipanalog datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8602834765829447680) (22 pp, sha256 `f22cb16e7b686413`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ca-is3021w-datasheet.pdf)
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