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Initial commit: component/ca-is3021g

Ray ·244d77dc2b ·
2 files changed +186
README.mdadded+45
@@ -0,0 +1,45 @@+# CA-IS3021G++**Chipanalog** · I2C Isolators · SOIC-8-300mil++CA-IS3021G from Chipanalog, in a SOIC-8-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VDDA | power_in | A-side power supply input with 3.0V to 5.5V operating range. |+| 2 | SDAA | bidirectional | A-side bidirectional data line, open-drain output with 3.5mA maximum sink current at 40pF load capacity. |+| 3 | SCLA | input | A-side clock input with Schmitt trigger and 40pF maximum load capacitance. |+| 4 | GNDA | power_in | A-side ground reference. |+| 5 | GNDB | power_in | B-side ground reference. |+| 6 | SCLB | output | B-side clock output with open-drain configuration, 35mA maximum sink current at 400pF load capacity. |+| 7 | SDAB | bidirectional | B-side bidirectional data line, open-drain output with 35mA maximum sink current at 400pF load capacity. |+| 8 | VDDB | power_in | B-side power supply input with 3.0V to 5.5V operating range. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Chipanalog |+| Package | SOIC-8-300mil |+| Category | Signal Isolation Devices |+| Pins | 8 |++## CAD (KiCad official)++- Symbol: `CA-IS3021G`+- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`+- 3D model: SOIC-8-300mil (KiCad packages3D, STEP)+- 3D model files: `ca-is3021g-etched.step` / `ca-is3021g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ca-is3021g.step` / `ca-is3021g.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Chipanalog datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590904806171095040) (22 pp, sha256 `f22cb16e7b686413`, retrieved 2026-09-18, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ca-is3021g-datasheet.pdf)
page.jsonadded+141
@@ -0,0 +1,141 @@+{+  "slug": "ca-is3021g",+  "version": "0.1.0",+  "type": "component",+  "description": "Chipanalog I2C Isolators, SOIC-8-300mil. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "signal isolation devices",+    "ca-is3021g",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "ca-is3021g.kicad_sym",+    "ca-is3021g.kicad_mod",+    "ca-is3021g.glb",+    "ca-is3021g.step",+    "ca-is3021g.lbr",+    "docs/hero.png",+    "docs/ca-is3021g-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "component": {+    "mpn": "CA-IS3021G",+    "manufacturer": "Chipanalog",+    "package": "SOIC-8-300mil",+    "pin_count": 8,+    "category": "Signal Isolation Devices",+    "subcategory": "I2C Isolators",+    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590904806171095040",+    "parts": {+      "symbol": "ca-is3021g.kicad_sym",+      "footprint": "ca-is3021g.kicad_mod",+      "model_3d": "ca-is3021g-etched.glb",+      "model_3d_plain": "ca-is3021g.glb",+      "model_3d_step": "ca-is3021g-etched.step",+      "model_3d_step_plain": "ca-is3021g.step",+      "lbr": "ca-is3021g.lbr"+    },+    "distributor_links": {+      "lcsc": "C7422514"+    },+    "pins": [+      {+        "number": "1",+        "name": "VDDA",+        "type": "power_in",+        "description": "A-side power supply input with 3.0V to 5.5V operating range."+      },+      {+        "number": "2",+        "name": "SDAA",+        "type": "bidirectional",+        "description": "A-side bidirectional data line, open-drain output with 3.5mA maximum sink current at 40pF load capacity."+      },+      {+        "number": "3",+        "name": "SCLA",+        "type": "input",+        "description": "A-side clock input with Schmitt trigger and 40pF maximum load capacitance."+      },+      {+        "number": "4",+        "name": "GNDA",+        "type": "power_in",+        "description": "A-side ground reference."+      },+      {+        "number": "5",+        "name": "GNDB",+        "type": "power_in",+        "description": "B-side ground reference."+      },+      {+        "number": "6",+        "name": "SCLB",+        "type": "output",+        "description": "B-side clock output with open-drain configuration, 35mA maximum sink current at 400pF load capacity."+      },+      {+        "number": "7",+        "name": "SDAB",+        "type": "bidirectional",+        "description": "B-side bidirectional data line, open-drain output with 35mA maximum sink current at 400pF load capacity."+      },+      {+        "number": "8",+        "name": "VDDB",+        "type": "power_in",+        "description": "B-side power supply input with 3.0V to 5.5V operating range."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.2",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.2",+        "primary_model": "claude-haiku-4-5-20251001",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-4-6",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [],+        "pages_sent": 22,+        "cost_usd": 0.2516,+        "at": "2026-09-18T02:02:40"+      },+      "datasheet": {+        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590904806171095040",+        "pages": 22,+        "sha256": "f22cb16e7b686413",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 8,+        "described": 8,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file