CA-IF4420S

@@ -0,0 +1,48 @@+# CA-IF4420S++**Chipanalog** · RS-485/RS-422 ICs · SOIC-8++CA-IF4420S from Chipanalog, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | TXD | input | Transmit data input. TXD high drives the CAN bus recessive; TXD low drives the bus dominant. Internally pulled up to VIO. |+| 2 | GND | power_in | Ground reference. |+| 3 | VCC | power_in | 5 V bus-side supply input (4.5 V to 5.5 V recommended). Bypass with a 0.1 µF ceramic capacitor placed close to the pin between VCC and GND. |+| 4 | RXD | output | Receiver data output. High when the CAN bus is recessive, low when the bus is dominant. Output is referenced to VIO. |+| 5 | VIO | power_in | I/O supply for logic-level translation (1.7 V to 5.5 V). Sets the reference for TXD, RXD, and POL logic thresholds so the transceiver can interface with 1.8 V / 2.5 V / 3.3 V / 5 V controllers. |+| 6 | CANL | bidirectional | Low-side CAN bus I/O. Tolerates ±58 V bus fault voltage and ±30 V receiver common-mode range. |+| 7 | CANH | bidirectional | High-side CAN bus I/O. Tolerates ±58 V bus fault voltage and ±30 V receiver common-mode range. |+| 8 | POL | input | Polarity control input. POL = low selects normal (default) CAN bus polarity; POL = high inverts the CANH/CANL polarity. Referenced to VIO logic levels. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Chipanalog |+| Package | SOIC-8 |+| Category | Comm/UART |+| Pins | 8 |++## Ordering variants++- `CA-IF4420S`++## CAD (KiCad official)++- Symbol: `CA-IF4420S`+- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`+- 3D model: SOIC-8 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Chipanalog datasheet](docs/ca-if4420s-datasheet.pdf) (20 pp, sha256 `b6a5642576e922f3`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ca-if4420s-datasheet.pdf)

@@ -0,0 +1,34 @@+{+  "slug": "ca-if4420s",+  "version": "0.1.0",+  "type": "component",+  "description": "Chipanalog RS-485/RS-422 ICs, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "comm-uart",+    "ca-if4420s"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "ca-if4420s.kicad_sym",+    "ca-if4420s.kicad_mod",+    "ca-if4420s.glb",+    "ca-if4420s.step",+    "ca-if4420s.lbr",+    "docs/hero.png",+    "docs/ca-if4420s-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file