component
CA-IF4420S
Public Made by Adomby adom
Chipanalog RS-485/RS-422 ICs, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+116−8@@ -1,13 +1,126 @@ {+ "schema_version": 1,+ "type": "component", "slug": "ca-if4420s",+ "title": "CA-IF4420S",+ "brief": "Chipanalog RS-485/RS-422 ICs, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "Chipanalog RS-485/RS-422 ICs, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "comm-uart", "ca-if4420s" ],+ "component": {+ "mpn": "CA-IF4420S",+ "manufacturer": "Chipanalog",+ "package": "SOIC-8",+ "pin_count": 8,+ "category": "Comm/UART",+ "subcategory": "RS-485/RS-422 ICs",+ "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2403291734_Chipanalog-CA-IF4420S_C7422518.pdf",+ "parts": {+ "symbol": "ca-if4420s.kicad_sym",+ "footprint": "ca-if4420s.kicad_mod",+ "model_3d": "ca-if4420s.glb",+ "model_3d_step": "ca-if4420s.step",+ "lbr": "ca-if4420s.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "TXD",+ "type": "input",+ "description": "Transmit data input. TXD high drives the CAN bus recessive; TXD low drives the bus dominant. Internally pulled up to VIO."+ },+ {+ "number": "2",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference."+ },+ {+ "number": "3",+ "name": "VCC",+ "type": "power_in",+ "description": "5 V bus-side supply input (4.5 V to 5.5 V recommended). Bypass with a 0.1 \u00b5F ceramic capacitor placed close to the pin between VCC and GND."+ },+ {+ "number": "4",+ "name": "RXD",+ "type": "output",+ "description": "Receiver data output. High when the CAN bus is recessive, low when the bus is dominant. Output is referenced to VIO."+ },+ {+ "number": "5",+ "name": "VIO",+ "type": "power_in",+ "description": "I/O supply for logic-level translation (1.7 V to 5.5 V). Sets the reference for TXD, RXD, and POL logic thresholds so the transceiver can interface with 1.8 V / 2.5 V / 3.3 V / 5 V controllers."+ },+ {+ "number": "6",+ "name": "CANL",+ "type": "bidirectional",+ "description": "Low-side CAN bus I/O. Tolerates \u00b158 V bus fault voltage and \u00b130 V receiver common-mode range."+ },+ {+ "number": "7",+ "name": "CANH",+ "type": "bidirectional",+ "description": "High-side CAN bus I/O. Tolerates \u00b158 V bus fault voltage and \u00b130 V receiver common-mode range."+ },+ {+ "number": "8",+ "name": "POL",+ "type": "input",+ "description": "Polarity control input. POL = low selects normal (default) CAN bus polarity; POL = high inverts the CANH/CANL polarity. Referenced to VIO logic levels."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2403291734_Chipanalog-CA-IF4420S_C7422518.pdf",+ "pages": 20,+ "sha256": "b6a5642576e922f3",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 8,+ "described": 8,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Chipanalog",+ "Package": "SOIC-8",+ "Category": "Comm/UART",+ "Pins": "8"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "ca-if4420s"+ ],+ "discovery_pitch": "CA-IF4420S (Chipanalog) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +138,5 @@ "docs/ca-if4420s-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }