component
C8051F340-GQR
Public Made by Adomby adom
SKYWORKS SILICON LABS Microcontrollers (MCU/MPU/SOC), TQFP-48(7x7). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
Publish 0.1.0
6 files changed
+17799
diff truncated
c8051f340-gqr.glbadded⋯ 1 unchanged line ⋯
c8051f340-gqr.kicad_modadded+630@@ -0,0 +1,630 @@+(footprint "TQFP-48_7x7mm_P0.5mm"+ (version 20260206)+ (generator "kicad-footprint-generator")+ (layer "F.Cu")+ (descr "TQFP, 48 Pin (JEDEC MS-026 variation ABC, 1.00mm body thickness, https://www.jedec.org/document_search?search_api_views_fulltext=MS-026, https://ww1.microchip.com/downloads/en/PackagingSpec/00000049BZ.pdf#page=666)")+ (tags "TQFP QFP P48GA-50-HAA-2 pkg_3304 PTQP0048KC-A C48-11 PFB0048A")+ (property "Reference" "REF**"+ (at 0 -5.85 0)+ (layer "F.SilkS")+ (effects+ (font+ (size 1 1)+ (thickness 0.15)+ )+ )+ )+ (property "Value" "TQFP-48_7x7mm_P0.5mm"+ (at 0 5.85 0)+ (layer "F.Fab")+ (effects+ (font+ (size 1 1)+ (thickness 0.15)+ )+ )+ )+ (property "KiLib_Generator" "package/gullwing"+ (at 0 0 0)+ (layer "F.SilkS")+ (hide yes)+ (effects+ (font+ (size 1 1)+ (thickness 0.15)+ )+ )+ )+ (attr smd)+ (duplicate_pad_numbers_are_jumpers no)+ (fp_line+ (start -3.61 -3.61)+ (end -3.16 -3.61)+ (stroke+ (width 0.12)+ (type solid)+ )+ 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gate="G$1" pin="P4.0" pad="22"/>+ <connect gate="G$1" pin="P3.7" pad="23"/>+ <connect gate="G$1" pin="P3.6" pad="24"/>+ <connect gate="G$1" pin="P0.6" pad="48"/>+ <connect gate="G$1" pin="P0.7" pad="47"/>+ <connect gate="G$1" pin="P1.0" pad="46"/>+ <connect gate="G$1" pin="P1.1" pad="45"/>+ <connect gate="G$1" pin="P1.2" pad="44"/>+ <connect gate="G$1" pin="P1.3" pad="43"/>+ <connect gate="G$1" pin="P1.4" pad="42"/>+ <connect gate="G$1" pin="P1.5" pad="41"/>+ <connect gate="G$1" pin="P1.6" pad="40"/>+ <connect gate="G$1" pin="P1.7" pad="39"/>+ <connect gate="G$1" pin="P2.0" pad="38"/>+ <connect gate="G$1" pin="P2.1" pad="37"/>+ <connect gate="G$1" pin="P2.2" pad="36"/>+ <connect gate="G$1" pin="P2.3" pad="35"/>+ <connect gate="G$1" pin="P2.4" pad="34"/>+ <connect gate="G$1" pin="P2.5" pad="33"/>+ <connect gate="G$1" pin="P2.6" pad="32"/>+ <connect gate="G$1" pin="P2.7" pad="31"/>+ <connect gate="G$1" pin="P3.0" pad="30"/>+ <connect gate="G$1" pin="P3.1" pad="29"/>+ <connect gate="G$1" pin="P3.2" pad="28"/>+ <connect gate="G$1" pin="P3.3" pad="27"/>+ <connect gate="G$1" pin="P3.4" pad="26"/>+ <connect gate="G$1" pin="P3.5" pad="25"/>+ </connects>+ <technologies><technology name=""/></technologies>+ </device>+ </devices>+</deviceset>+</devicesets>+</library>+</drawing>+</eagle>
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Please refer to+ * https://gitlab.com/kicad/libraries/kicad-packages3D/-/blob/master/LICENSE.md for further clarification+ * of the exception.+ *+ * Disclaimer of Warranties and Limitation of Liability.+ * These libraries are provided in the hope that they will be useful, but are provided without warranty of any kind, express or implied.+ * USE 3D CAD DATA AT YOUR OWN RISK+ * DO NOT RELY UPON ANY INFORMATION FOUND HERE WITHOUT INDEPENDENT VERIFICATION.+ */++FILE_DESCRIPTION(+/* description */ ('model of TQFP-48_7x7mm_P0.5mm'),+/* implementation_level */ '2;1');++FILE_NAME(+/* name */ 'TQFP-48_7x7mm_P0.5mm.step',+/* time_stamp */ '1970-01-01T00:00:00',+/* author */ ('KiCAD','kicad'),+/* organization */ ('OCCT'),+/* preprocessor_version */ '',+/* originating_system */ 'KiCAD',+/* authorisation */ '');++FILE_SCHEMA(('AUTOMOTIVE_DESIGN { 1 0 10303 214 1 1 1 1 }'));+ENDSEC;++DATA;+#1=APPLICATION_PROTOCOL_DEFINITION('international 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2=STYLED_ITEM('color',(#14235),#7096);+#14553=STYLED_ITEM('color',(#14235),#7156);+#14554=STYLED_ITEM('color',(#14235),#7172);+#14555=STYLED_ITEM('color',(#14222),#7225);+#14556=STYLED_ITEM('color',(#14235),#7236);+#14557=STYLED_ITEM('color',(#14235),#7296);+#14558=STYLED_ITEM('color',(#14235),#7312);+#14559=STYLED_ITEM('color',(#14222),#7365);+#14560=STYLED_ITEM('color',(#14235),#7373);+#14561=STYLED_ITEM('color',(#14235),#7431);+#14562=STYLED_ITEM('color',(#14235),#7447);+#14563=STYLED_ITEM('color',(#14235),#7495);+#14564=STYLED_ITEM('color',(#14235),#7560);+#14565=STYLED_ITEM('color',(#14235),#7576);+#14566=STYLED_ITEM('color',(#14222),#7624);+#14567=STYLED_ITEM('color',(#14235),#7634);+#14568=STYLED_ITEM('color',(#14235),#7694);+#14569=STYLED_ITEM('color',(#14235),#7710);+#14570=STYLED_ITEM('color',(#14222),#7763);+#14571=STYLED_ITEM('color',(#14235),#7774);+#14572=STYLED_ITEM('color',(#14235),#7834);+#14573=STYLED_ITEM('color',(#14235),#7850);+#14574=STYLED_ITEM('color',(#14222),#7903);+#14575=STYLED_ITEM('color',(#14235),#7914);+#14576=STYLED_ITEM('color',(#14235),#7974);+#14577=STYLED_ITEM('color',(#14235),#7990);+#14578=STYLED_ITEM('color',(#14222),#8043);+#14579=STYLED_ITEM('color',(#14235),#8054);+#14580=STYLED_ITEM('color',(#14235),#8114);+#14581=STYLED_ITEM('color',(#14235),#8130);+#14582=STYLED_ITEM('color',(#14222),#8183);+#14583=STYLED_ITEM('color',(#14235),#8194);+#14584=STYLED_ITEM('color',(#14235),#8254);+#14585=STYLED_ITEM('color',(#14235),#8270);+#14586=STYLED_ITEM('color',(#14222),#8323);+#14587=STYLED_ITEM('color',(#14235),#8334);+#14588=STYLED_ITEM('color',(#14235),#8394);+#14589=STYLED_ITEM('color',(#14235),#8410);+#14590=STYLED_ITEM('color',(#14222),#8463);+#14591=STYLED_ITEM('color',(#14235),#8474);+#14592=STYLED_ITEM('color',(#14235),#8534);+#14593=STYLED_ITEM('color',(#14235),#8550);+#14594=STYLED_ITEM('color',(#14222),#8603);+#14595=STYLED_ITEM('color',(#14235),#8614);+#14596=STYLED_ITEM('color',(#14235),#8674);+#14597=STYLED_ITEM('color',(#14235),#8690);+#14598=STYLED_ITEM('color',(#14222),#8743);+#14599=STYLED_ITEM('color',(#14235),#8754);+#14600=STYLED_ITEM('color',(#14235),#8814);+#14601=STYLED_ITEM('color',(#14235),#8830);+#14602=STYLED_ITEM('color',(#14222),#8883);+#14603=STYLED_ITEM('color',(#14235),#8894);+#14604=STYLED_ITEM('color',(#14235),#8954);+#14605=STYLED_ITEM('color',(#14235),#8970);+#14606=STYLED_ITEM('color',(#14222),#9023);+#14607=STYLED_ITEM('color',(#14235),#9034);+#14608=STYLED_ITEM('color',(#14235),#9094);+#14609=STYLED_ITEM('color',(#14235),#9110);+#14610=STYLED_ITEM('color',(#14222),#9163);+#14611=STYLED_ITEM('color',(#14235),#9184);+#14612=STYLED_ITEM('color',(#14235),#9252);+#14613=STYLED_ITEM('color',(#14235),#9268);+#14614=STYLED_ITEM('color',(#14222),#9321);+#14615=STYLED_ITEM('color',(#14235),#9337);+#14616=STYLED_ITEM('color',(#14235),#9397);+#14617=STYLED_ITEM('color',(#14235),#9413);+#14618=STYLED_ITEM('color',(#14222),#9466);+#14619=STYLED_ITEM('color',(#14235),#9482);+#14620=STYLED_ITEM('color',(#14235),#9542);+#14621=STYLED_ITEM('color',(#14235),#9558);+#14622=STYLED_ITEM('color',(#14222),#9611);+#14623=STYLED_ITEM('color',(#14235),#9627);+#14624=STYLED_ITEM('color',(#14235),#9687);+#14625=STYLED_ITEM('color',(#14235),#9703);+#14626=STYLED_ITEM('color',(#14222),#9756);+#14627=STYLED_ITEM('color',(#14235),#9772);+#14628=STYLED_ITEM('color',(#14235),#9832);+#14629=STYLED_ITEM('color',(#14235),#9848);+#14630=STYLED_ITEM('color',(#14222),#9901);+#14631=STYLED_ITEM('color',(#14235),#9917);+#14632=STYLED_ITEM('color',(#14235),#9977);+#14633=STYLED_ITEM('color',(#14235),#9993);+#14634=STYLED_ITEM('color',(#14222),#10046);+#14635=STYLED_ITEM('color',(#14235),#10062);+#14636=STYLED_ITEM('color',(#14235),#10122);+#14637=STYLED_ITEM('color',(#14235),#10138);+#14638=STYLED_ITEM('color',(#14222),#10191);+#14639=STYLED_ITEM('color',(#14235),#10207);+#14640=STYLED_ITEM('color',(#14235),#10267);+#14641=STYLED_ITEM('color',(#14235),#10283);+#14642=STYLED_ITEM('color',(#14222),#10336);+#14643=STYLED_ITEM('color',(#14235),#10352);+#14644=STYLED_ITEM('color',(#14235),#10412);+#14645=STYLED_ITEM('color',(#14235),#10428);+#14646=STYLED_ITEM('color',(#14222),#10481);+#14647=STYLED_ITEM('color',(#14235),#10497);+#14648=STYLED_ITEM('color',(#14235),#10557);+#14649=STYLED_ITEM('color',(#14235),#10573);+#14650=STYLED_ITEM('color',(#14222),#10626);+#14651=STYLED_ITEM('color',(#14235),#10642);+#14652=STYLED_ITEM('color',(#14235),#10702);+#14653=STYLED_ITEM('color',(#14235),#10718);+#14654=STYLED_ITEM('color',(#14222),#10771);+#14655=STYLED_ITEM('color',(#14235),#10787);+#14656=STYLED_ITEM('color',(#14235),#10847);+#14657=STYLED_ITEM('color',(#14235),#10863);+#14658=STYLED_ITEM('color',(#14235),#10914);+#14659=STYLED_ITEM('color',(#14235),#10924);+#14660=STYLED_ITEM('color',(#14235),#10936);+#14661=STYLED_ITEM('color',(#14235),#10948);+#14662=STYLED_ITEM('color',(#14235),#10960);+#14663=STYLED_ITEM('color',(#14235),#10972);+#14664=STYLED_ITEM('color',(#14235),#10984);+#1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Memory Map)>> endobj 22944 0 obj<</Parent 22942 0 R/Dest(G11.1165447)/Prev 22949 0 R/Title(SFR Definition 9.6. B: B Register)>> endobj 22945 0 obj<</First 22946 0 R/Parent 22840 0 R/Next 22942 0 R/Dest(G11.1026962)/Count -3/Last 22947 0 R/Prev 22841 0 R/Title(9.1. Instruction Set)>> endobj 22946 0 obj<</Parent 22945 0 R/Next 22948 0 R/Dest(G11.1026964)/Title(9.1.1. Instruction and CPU Timing)>> endobj 22947 0 obj<</Parent 22945 0 R/Dest(G11.1166227)/Prev 22948 0 R/Title(Table 9.1. CIP-51 Instruction Set Summary)>> endobj 22948 0 obj<</Parent 22945 0 R/Next 22947 0 R/Dest(G11.1166213)/Prev 22946 0 R/Title(9.1.2. MOVX Instruction and Program Memory)>> endobj 22949 0 obj<</Parent 22942 0 R/Next 22944 0 R/Dest(G11.1043801)/Prev 22950 0 R/Title(SFR Definition 9.5. ACC: Accumulator)>> endobj 22950 0 obj<</Parent 22942 0 R/Next 22949 0 R/Dest(G11.1165418)/Prev 22951 0 R/Title(SFR Definition 9.4. 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Internal XRAM Only)>> endobj 23015 0 obj<</Parent 22831 0 R/Next 22997 0 R/Dest(G15.1051244)/Prev 23016 0 R/Title(Figure 13.10. Multiplexed 8-bit MOVX with Bank Select Timing)>> endobj 23016 0 obj<</Parent 22831 0 R/Next 23015 0 R/Dest(G15.1051232)/Prev 23017 0 R/Title(Figure 13.9. Multiplexed 8-bit MOVX without Bank Select Timing)>> endobj 23017 0 obj<</Parent 22831 0 R/Next 23016 0 R/Dest(G15.1051218)/Prev 23018 0 R/Title(Figure 13.8. Multiplexed 16-bit MOVX Timing)>> endobj 23018 0 obj<</Parent 22831 0 R/Next 23017 0 R/Dest(G15.1034128)/Prev 23019 0 R/Title(13.7.2. Multiplexed Mode)>> endobj 23019 0 obj<</Parent 22831 0 R/Next 23018 0 R/Dest(G15.1051198)/Prev 23020 0 R/Title(Figure 13.7. Non-multiplexed 8-bit MOVX with Bank Select Timing)>> endobj 23020 0 obj<</Parent 22831 0 R/Next 23019 0 R/Dest(G15.1051182)/Prev 23021 0 R/Title(Figure 13.6. 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Oscillator Electrical Characteristics)>> endobj 23027 0 obj<</First 23028 0 R/Parent 22826 0 R/Next 22828 0 R/Dest(G16.1044059)/Count -1/Last 23028 0 R/Prev 23029 0 R/Title(14.4. 4x Clock Multiplier)>> endobj 23028 0 obj<</Parent 23027 0 R/Dest(G16.1044197)/Title(SFR Definition 14.5. CLKMUL: Clock Multiplier Control)>> endobj 23029 0 obj<</First 23030 0 R/Parent 22826 0 R/Next 23027 0 R/Dest(G16.1053462)/Count -5/Last 23031 0 R/Prev 23032 0 R/Title(14.3. External Oscillator Drive Circuit)>> endobj 23030 0 obj<</Parent 23029 0 R/Next 23041 0 R/Dest(G16.1045437)/Title(14.3.1. Clocking Timers Directly Through the External Oscillator)>> endobj 23031 0 obj<</Parent 23029 0 R/Dest(G16.1036458)/Prev 23039 0 R/Title(SFR Definition 14.4. OSCXCN: External Oscillator Control)>> endobj 23032 0 obj<</First 23033 0 R/Parent 22826 0 R/Next 23029 0 R/Dest(G16.1053456)/Count -2/Last 23034 0 R/Prev 23035 0 R/Title(14.2. Programmable Internal Low-Frequency \(L-F\) Oscillator)>> endobj 23033 0 obj<</Parent 23032 0 R/Next 23034 0 R/Dest(G16.1053487)/Title(14.2.1. Calibrating the Internal L-F Oscillator)>> endobj 23034 0 obj<</Parent 23032 0 R/Dest(G16.1053726)/Prev 23033 0 R/Title(SFR Definition 14.3. OSCLCN: Internal L-F Oscillator Control)>> endobj 23035 0 obj<</First 23036 0 R/Parent 22826 0 R/Next 23032 0 R/Dest(G16.1034789)/Count -3/Last 23037 0 R/Prev 22827 0 R/Title(14.1. Programmable Internal High-Frequency \(H-F\) Oscillator)>> endobj 23036 0 obj<</Parent 23035 0 R/Next 23038 0 R/Dest(G16.1044621)/Title(14.1.1. Internal H-F Oscillator Suspend Mode)>> endobj 23037 0 obj<</Parent 23035 0 R/Dest(G16.1053381)/Prev 23038 0 R/Title(SFR Definition 14.2. OSCICL: Internal H-F Oscillator Calibration)>> endobj 23038 0 obj<</Parent 23035 0 R/Next 23037 0 R/Dest(G16.1056465)/Prev 23036 0 R/Title(SFR Definition 14.1. OSCICN: Internal H-F Oscillator Control)>> endobj 23039 0 obj<</Parent 23029 0 R/Next 23031 0 R/Dest(G16.1044419)/Prev 23040 0 R/Title(14.3.4. External Capacitor Example)>> endobj 23040 0 obj<</Parent 23029 0 R/Next 23039 0 R/Dest(G16.1044408)/Prev 23041 0 R/Title(14.3.3. External RC Example)>> endobj 23041 0 obj<</Parent 23029 0 R/Next 23040 0 R/Dest(G16.1044393)/Prev 23030 0 R/Title(14.3.2. External Crystal Example)>> endobj 23042 0 obj<</Parent 22828 0 R/Next 23026 0 R/Dest(G16.1044360)/Prev 23043 0 R/Title(SFR Definition 14.6. CLKSEL: Clock Select)>> endobj 23043 0 obj<</Parent 22828 0 R/Next 23042 0 R/Dest(G16.1044203)/Prev 23025 0 R/Title(14.5.2. USB Clock Selection)>> endobj 23044 0 obj<</Parent 22825 0 R/Next 23071 0 R/Dest(G17.1056360)/Title(SFR Definition 15.4. P0: Port0 Latch)>> endobj 23045 0 obj<</Parent 22825 0 R/Dest(G17.1033661)/Prev 23054 0 R/Title(Table 15.1. Port I/O DC Electrical Characteristics)>> endobj 23046 0 obj<</First 23047 0 R/Parent 22823 0 R/Next 22825 0 R/Dest(G17.1029313)/Count -3/Last 23048 0 R/Prev 23049 0 R/Title(15.2. Port I/O Initialization)>> endobj 23047 0 obj<</Parent 23046 0 R/Next 23053 0 R/Dest(G17.1033397)/Title(SFR Definition 15.1. XBR0: Port I/O Crossbar Register 0)>> endobj 23048 0 obj<</Parent 23046 0 R/Dest(G17.1059930)/Prev 23053 0 R/Title(SFR Definition 15.3. XBR2: Port I/O Crossbar Register 2)>> endobj 23049 0 obj<</First 23050 0 R/Parent 22823 0 R/Next 23046 0 R/Dest(G17.1029308)/Count -2/Last 23051 0 R/Prev 23052 0 R/Title(15.1. Priority Crossbar Decoder)>> endobj 23050 0 obj<</Parent 23049 0 R/Next 23051 0 R/Dest(G17.1059894)/Title(Figure 15.3. Crossbar Priority Decoder with No Pins Skipped)>> endobj 23051 0 obj<</Parent 23049 0 R/Dest(G17.1059909)/Prev 23050 0 R/Title(Figure 15.4. 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Configuring Endpoints1-3)>> endobj 23078 0 obj<</First 23079 0 R/Parent 22820 0 R/Next 23077 0 R/Dest(G18.1061102)/Count -5/Last 23080 0 R/Prev 23081 0 R/Title(16.10. Endpoint0)>> endobj 23079 0 obj<</Parent 23078 0 R/Next 23116 0 R/Dest(G18.1061315)/Title(16.10.1. Endpoint0 SETUP Transactions)>> endobj 23080 0 obj<</Parent 23078 0 R/Dest(G18.1075384)/Prev 23114 0 R/Title(USB Register Definition 16.18. E0CNT: USB0 Endpoint 0 Data Count)>> endobj 23081 0 obj<</Parent 22820 0 R/Next 23078 0 R/Dest(G18.1053490)/Prev 23082 0 R/Title(16.9. The Serial Interface Engine)>> endobj 23082 0 obj<</First 23083 0 R/Parent 22820 0 R/Next 23081 0 R/Dest(G18.1057771)/Count -6/Last 23084 0 R/Prev 23085 0 R/Title(16.8. Interrupts)>> endobj 23083 0 obj<</Parent 23082 0 R/Next 23113 0 R/Dest(G18.1075275)/Title(USB Register Definition 16.11. IN1INT: USB0 IN Endpoint Interrupt)>> endobj 23084 0 obj<</Parent 23082 0 R/Dest(G18.1075302)/Prev 23110 0 R/Title(USB Register Definition 16.16. CMIE: USB0 Common Interrupt Enable)>> endobj 23085 0 obj<</First 23086 0 R/Parent 22820 0 R/Next 23082 0 R/Dest(G18.1058176)/Count -3/Last 23087 0 R/Prev 23088 0 R/Title(16.7. Function Configuration and Control)>> endobj 23086 0 obj<</Parent 23085 0 R/Next 23109 0 R/Dest(G18.1058844)/Title(USB Register Definition 16.8. POWER: USB0 Power)>> endobj 23087 0 obj<</Parent 23085 0 R/Dest(G18.1075236)/Prev 23109 0 R/Title(USB Register Definition 16.10. FRAMEH: USB0 Frame Number High)>> endobj 23088 0 obj<</First 23089 0 R/Parent 22820 0 R/Next 23085 0 R/Dest(G18.1058039)/Count -1/Last 23089 0 R/Prev 23090 0 R/Title(16.6. Function Addressing)>> endobj 23089 0 obj<</Parent 23088 0 R/Dest(G18.1075220)/Title(USB Register Definition 16.7. FADDR: USB0 Function Address)>> endobj 23090 0 obj<</First 23091 0 R/Parent 22820 0 R/Next 23088 0 R/Dest(G18.1050536)/Count -6/Last 23092 0 R/Prev 23093 0 R/Title(16.5. FIFO Management)>> endobj 23091 0 obj<</Parent 23090 0 R/Next 23108 0 R/Dest(G18.1075193)/Title(Figure 16.3. USB FIFO Allocation)>> endobj 23092 0 obj<</Parent 23090 0 R/Dest(G18.1049645)/Prev 23105 0 R/Title(USB Register Definition 16.6. FIFOn: USB0 Endpoint FIFO Access)>> endobj 23093 0 obj<</First 23094 0 R/Parent 22820 0 R/Next 23090 0 R/Dest(G18.1050580)/Count -1/Last 23094 0 R/Prev 23095 0 R/Title(16.4. USB Clock Configuration)>> endobj 23094 0 obj<</Parent 23093 0 R/Dest(G18.1070378)/Title(USB Register Definition 16.5. CLKREC: Clock Recovery Control)>> endobj 23095 0 obj<</First 23096 0 R/Parent 22820 0 R/Next 23093 0 R/Dest(G18.1049709)/Count -5/Last 23097 0 R/Prev 23098 0 R/Title(16.3. USB Register Access)>> endobj 23096 0 obj<</Parent 23095 0 R/Next 23104 0 R/Dest(G18.1075097)/Title(Figure 16.2. USB0 Register Access Scheme)>> endobj 23097 0 obj<</Parent 23095 0 R/Dest(G18.1075131)/Prev 23102 0 R/Title(USB Register Definition 16.4. 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SMB0CF: SMBus Clock/Configuration)>> endobj 23145 0 obj<</Parent 23128 0 R/Next 23144 0 R/Dest(G19.1053967)/Prev 23146 0 R/Title(Table 17.2. Minimum SDA Setup and Hold Times)>> endobj 23146 0 obj<</Parent 23128 0 R/Next 23145 0 R/Dest(G19.1080693)/Prev 23147 0 R/Title(Figure 17.4. Typical SMBus SCL Generation)>> endobj 23147 0 obj<</Parent 23128 0 R/Next 23146 0 R/Dest(G19.1049456)/Prev 23129 0 R/Title(Table 17.1. SMBus Clock Source Selection)>> endobj 23148 0 obj<</Parent 23125 0 R/Next 23127 0 R/Dest(G19.1035931)/Prev 23149 0 R/Title(17.5.4. Slave Transmitter Mode)>> endobj 23149 0 obj<</Parent 23125 0 R/Next 23148 0 R/Dest(G19.1080797)/Prev 23150 0 R/Title(Figure 17.7. Typical Slave Receiver Sequence)>> endobj 23150 0 obj<</Parent 23125 0 R/Next 23149 0 R/Dest(G19.1035887)/Prev 23151 0 R/Title(17.5.3. Slave Receiver Mode)>> endobj 23151 0 obj<</Parent 23125 0 R/Next 23150 0 R/Dest(G19.1080785)/Prev 23152 0 R/Title(Figure 17.6. Typical Master Receiver Sequence)>> endobj 23152 0 obj<</Parent 23125 0 R/Next 23151 0 R/Dest(G19.1050164)/Prev 23153 0 R/Title(17.5.2. Master Receiver Mode)>> endobj 23153 0 obj<</Parent 23125 0 R/Next 23152 0 R/Dest(G19.1080774)/Prev 23126 0 R/Title(Figure 17.5. Typical Master Transmitter Sequence)>> endobj 23154 0 obj<</Parent 22816 0 R/Next 23165 0 R/Dest(G20.1104846)/Title(Figure 18.6. UART Multi-Processor Mode Interconnect Diagram)>> endobj 23155 0 obj<</Parent 22816 0 R/Dest(G20.1101520)/Prev 23164 0 R/Title(Table 18.1. Timer Settings for Standard Baud Rates Using The Internal Oscillator)>> endobj 23156 0 obj<</First 23157 0 R/Parent 22814 0 R/Next 22816 0 R/Dest(G20.1035562)/Count -5/Last 23158 0 R/Prev 23159 0 R/Title(18.2. Operational Modes)>> endobj 23157 0 obj<</Parent 23156 0 R/Next 23163 0 R/Dest(G20.1104800)/Title(Figure 18.3. UART Interconnect Diagram)>> endobj 23158 0 obj<</Parent 23156 0 R/Dest(G20.1104835)/Prev 23161 0 R/Title(Figure 18.5. 9-Bit UART Timing Diagram)>> endobj 23159 0 obj<</First 23160 0 R/Parent 22814 0 R/Next 23156 0 R/Dest(G20.1035540)/Count -1/Last 23160 0 R/Prev 22815 0 R/Title(18.1. Enhanced Baud Rate Generation)>> endobj 23160 0 obj<</Parent 23159 0 R/Dest(G20.1104771)/Title(Figure 18.2. UART0 Baud Rate Logic)>> endobj 23161 0 obj<</Parent 23156 0 R/Next 23158 0 R/Dest(G20.1104821)/Prev 23162 0 R/Title(18.2.2. 9-Bit UART)>> endobj 23162 0 obj<</Parent 23156 0 R/Next 23161 0 R/Dest(G20.1104824)/Prev 23163 0 R/Title(Figure 18.4. 8-Bit UART Timing Diagram)>> endobj 23163 0 obj<</Parent 23156 0 R/Next 23162 0 R/Dest(G20.1036765)/Prev 23157 0 R/Title(18.2.1. 8-Bit UART)>> endobj 23164 0 obj<</Parent 22816 0 R/Next 23155 0 R/Dest(G20.1047663)/Prev 23165 0 R/Title(SFR Definition 18.2. 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UART1 Timing With Extra Bit)>> endobj 23171 0 obj<</First 23172 0 R/Parent 22811 0 R/Next 23168 0 R/Dest(G21.1035540)/Count -1/Last 23172 0 R/Prev 22812 0 R/Title(19.1. Baud Rate Generator)>> endobj 23172 0 obj<</Parent 23171 0 R/Dest(G21.1139443)/Title(Table 19.1. Baud Rate Generator Settings for Standard Baud Rates)>> endobj 23173 0 obj<</Parent 23168 0 R/Next 23170 0 R/Dest(G21.1138735)/Prev 23169 0 R/Title(Figure 19.3. UART1 Timing With Parity)>> endobj 23174 0 obj<</Parent 22813 0 R/Next 23167 0 R/Dest(G21.1120435)/Prev 23175 0 R/Title(SFR Definition 19.5. SBRLH1: UART1 Baud Rate Generator High Byte)>> endobj 23175 0 obj<</Parent 22813 0 R/Next 23174 0 R/Dest(G21.1120432)/Prev 23176 0 R/Title(SFR Definition 19.4. SBCON1: UART1 Baud Rate Generator Control)>> endobj 23176 0 obj<</Parent 22813 0 R/Next 23175 0 R/Dest(G21.1120429)/Prev 23177 0 R/Title(SFR Definition 19.3. SBUF1: UART1 Data Buffer)>> endobj 23177 0 obj<</Parent 22813 0 R/Next 23176 0 R/Dest(G21.1111386)/Prev 23178 0 R/Title(SFR Definition 19.2. SMOD1: UART1 Mode)>> endobj 23178 0 obj<</Parent 22813 0 R/Next 23177 0 R/Dest(G21.1035056)/Prev 23179 0 R/Title(SFR Definition 19.1. SCON1: UART1 Control)>> endobj 23179 0 obj<</Parent 22813 0 R/Next 23178 0 R/Dest(G21.1138778)/Prev 23180 0 R/Title(Figure 19.6. UART Multi-Processor Mode Interconnect Diagram)>> endobj 23180 0 obj<</Parent 22813 0 R/Next 23179 0 R/Dest(G21.1111020)/Prev 23181 0 R/Title(19.3.3. Multiprocessor Communications)>> endobj 23181 0 obj<</Parent 22813 0 R/Next 23180 0 R/Dest(G21.1110831)/Prev 23182 0 R/Title(19.3.2. Data Reception)>> endobj 23182 0 obj<</Parent 22813 0 R/Next 23181 0 R/Dest(G21.1110232)/Prev 23166 0 R/Title(19.3.1. Data Transmission)>> endobj 23183 0 obj<</Parent 22810 0 R/Next 23206 0 R/Dest(G22.1053263)/Title(SFR Definition 20.1. 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