component
C1812C124J1GACTU - KEMET
Public Made by Adomby adom
MLCC 0.12 uF +/-5 %, 100 V, C0G/NP0, 1812 (4532 metric)
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Component record for c1812c124j1gactu: files batch 1
20 files changed
+8570−2
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LICENSEadded+14@@ -0,0 +1,14 @@+C1812C124J1GACTU component page++Original Adom content on this page (README text, the KiCad symbol C1812C124J1GACTU.kicad_sym, the verification+drawings, the JSON records and the scripts in provenance/tools/) is licensed under the Creative+Commons Attribution 4.0 International License (CC-BY-4.0): https://creativecommons.org/licenses/by/4.0/++Third-party files keep their own terms and are not relicensed by this page:+- vendor/C1812C124J1GACTU-kemet-original.step is KEMET's 3D model for this part, downloaded from KEMET, under KEMET's terms.+ C1812C124J1GACTU.step and every model derived from it (package-reference.glb, c1812c124j1gactu-hero.glb, lod/*.glb, the body+ inside altium/C1812C124J1GACTU.PcbLib) are re-posed derivatives of that file and keep KEMET's terms.+- C_1812_4532Metric_C1812C124J1GACTU.kicad_mod is KiCad library content, CC-BY-SA 4.0 with the KiCad library exception+ (https://gitlab.com/kicad/libraries/kicad-footprints); the footprint inside C1812C124J1GACTU.lbr and altium/C1812C124J1GACTU.PcbLib keeps that license.+- docs/KEMET-C1003-C0G-2025-02-20.pdf and the page crops in docs/figures/ are KEMET documents, copyright of KEMET+ Electronics Corporation (YAGEO Group), included unchanged (or cropped) for reference.
README.md+194−2@@ -1,3 +1,195 @@-# C1812C124J1GACTU - KEMET+# C1812C124J1GACTU -MLCC 0.12 uF +/-5 %, 100 V, C0G/NP0, 1812 (4532 metric)+KEMET C1812C124J1GACTU: MLCC 0.12 uF +/-5 %, 100 V, C0G/NP0, 1812 (4532 metric). A commercial grade, class I multilayer ceramic chip capacitor from KEMET's C0G series+(KEMET is part of the YAGEO Group). C0G holds its capacitance against DC voltage, temperature and time, which makes it the+choice for timing, tuning, filters, snubbers and other circuits where the value must not move.++::adom-verified{src="/adom/c1812c124j1gactu/render/verification.json"}++| Field | Value |+|---|---|+| Manufacturer | KEMET Electronics Corporation (YAGEO Group) |+| Manufacturer part number | C1812C124J1GACTU |+| Type | MLCC, Class 1 (C0G / NP0), commercial grade |+| Capacitance | 0.12 uF (120 nF), +/-5 % (J) |+| Rated voltage | 100 V DC |+| Dielectric | C0G (NP0): 0 +/-30 ppm/C, -55 to +125 C |+| Package | 1812 (4532 metric), 4.50 x 3.20 x 1.40 mm (thickness code GH) |+| Marking | none (C0G parts are supplied unmarked) |+| Datasheet | [KEMET, Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs), C0G Dielectric, 10 to 250 VDC (Commercial Grade), C1003_C0G, 2/20/2025 (22 pages)](docs/KEMET-C1003-C0G-2025-02-20.pdf) |++## Why C0G: stable with voltage, temperature and time++The figures below are KEMET's, from the datasheet on this page:++- **Voltage.** "No capacitance change with respect to applied rated DC voltage" (p.2; the overview on p.1 says C0G+ "exhibits no change in capacitance with respect to time and voltage"). At 100 V this part is still 0.12 uF.+- **Temperature.** Capacitance change is limited to +/-30 ppm/C from -55 to +125 C, referenced to +25 C (p.1, p.4).+ Worked out from that limit: at most +/-0.3 % at +125 C and +/-0.24 % at -55 C.+- **Time.** Aging rate 0 % per decade hour (p.4), "no capacitance decay with time" (p.2).+- **No piezoelectric noise**, low ESR and ESL and high ripple current capability are listed as benefits (p.1).++By contrast, a class II X7R capacitor is allowed +/-15 % over -55 to +125 C (the EIA X7R definition), loses part of its+capacitance under DC bias, and ages over time; at a 100 V rating that bias loss can be large. That is the reason to+choose this C0G part over an X7R of the same value where the capacitance has to stay put: the cost is size, since 0.12 uF+at 100 V needs an 1812 case in C0G.++++++## Key specifications++| Parameter | Value | Datasheet page |+|---|---|---|+| Capacitance | 0.12 uF (120 nF) +/-5 % (code 124, J) | p.1 ordering information |+| Rated voltage | 100 V DC (voltage code 1) | p.1 |+| Dielectric | C0G (NP0), EIA Class I, temperature compensating | p.1 |+| Temperature coefficient | 0 +/-30 ppm/C from -55 to +125 C, referenced to +25 C and 0 V DC | p.1, p.4 |+| Voltage coefficient | no capacitance change with applied rated DC voltage | p.1, p.2 |+| Aging | 0 % (maximum capacitance loss per decade hour); no capacitance decay with time | p.2, p.4 |+| Dissipation factor | 0.1 % max at 25 C (1 kHz, 1.0 Vrms for parts above 1,000 pF) | p.4 |+| Insulation resistance | 1,000 MOhm x uF or 100 GOhm, whichever is lower: about 8.3 GOhm min for 0.12 uF (100 V applied, 25 C) | p.4 |+| Dielectric withstanding voltage | 250 % of rated voltage (250 V) for 5 +/-1 s, charge current up to 50 mA | p.4 |+| After life, humidity and moisture tests | capacitance shift 0.3 % or +/-0.25 pF max, DF 0.5 % max, IR 10 % of initial limit | p.4 |+| Operating temperature | -55 to +125 C | p.4 |+| Size | L 4.50 +/-0.30, W 3.20 +/-0.30, T 1.40 +/-0.15 (thickness code GH), B 0.60 +/-0.35, S 2.30 min (mm) | p.3, p.8, p.10 |+| Termination | 100 % matte tin over nickel barrier over copper (termination code C) | p.1, p.15 |+| Packaging (TU) | 7 inch reel, unmarked; embossed plastic tape 12 mm wide, 8 mm pitch; 1,000 pieces per reel | p.2, p.10, p.16 |+| Soldering | reflow only for 1812; matte Sn profile peaks at 260 C; up to three reflow passes | p.3, p.13 |+| Compliance | lead (Pb) free, RoHS and REACH compliant without exemptions | p.1, p.2 |+| Marking | none: C0G parts are supplied unmarked only | p.2, p.15 |++Page numbers refer to [KEMET C1003_C0G, 2/20/2025](docs/KEMET-C1003-C0G-2025-02-20.pdf).++## Ordering++| Distributor | Part number | Stock seen 2026-10-21 | Price seen |+|---|---|---|---|+| Mouser | [80-C1812C124J1G](https://www.mouser.com/ProductDetail/KEMET/C1812C124J1GACTU?qs=Fn3VdHBzkcnCFZmhvW0Uag%3D%3D) | 1,701 | $2.98 (1), $1.79 (100), lead time 266 days |+| DigiKey | [399-C1812C124J1GACTUTR-ND](https://www.digikey.com/en/products/detail/kemet/C1812C124J1GACTU/1874760) | 1,761 | $3.53 (1) |+| LCSC / JLCPCB | not listed | - | - |++Stock and prices are a snapshot from the Adom parts search on 2026-10-21; check the distributor before ordering. DigiKey lists+the part as Active. JLCPCB/LCSC search for C1812C124J1GACTU returned no part on 2026-10-21.++## Part number++C ceramic | 1812 case size | C standard series | 124 = 12 x 10^4 pF = 0.12 uF | J +/-5 % | 1 = 100 V | G = C0G |+A failure rate not applicable | C 100 % matte Sn termination | TU 7 inch reel, unmarked (datasheet p.1 and p.2). The+thickness is not in the part number: Table 1B (p.8) gives code GH for 0.12 uF at 100 V in 1812, and Table 2A (p.10)+gives GH = 1.40 +/-0.15 mm.++++## Manufacturer and resources++| Resource | Link |+|---|---|+| Product page | https://yageogroup.com/en/us/capacitors/ceramic/mlccs-smd/C1812C124J1GACTU.html (the KEMET address https://www.kemet.com/en/us/capacitors/ceramic/mlccs-smd/C1812C124J1GACTU.html redirects there) |+| Datasheet C1003_C0G, 2/20/2025 | [PDF on this page](docs/KEMET-C1003-C0G-2025-02-20.pdf) ([KEMET](https://content.kemet.com/datasheets/KEM_C1003_C0G_SMD.pdf), [YAGEO](https://yageogroup.com/content/datasheet/asset/file/KEM_C1003_C0G_SMD)) |+| 3D model (STEP) | [https://search.kemet.com/component-documentation/download/step/C1812C124J1GACTU.step](https://search.kemet.com/component-documentation/download/step/C1812C124J1GACTU.step) (copy under `vendor/`) |+| KEMET K-SIM simulation (impedance, ESR, temperature rise) | https://ksim3.kemet.com/capacitor-simulation?pn=C1812C124J1GACTU |+| Flexible termination version | KEMET product bulletin C1062_C0G_FT-CAP_SMD (datasheet p.1 note 1) |++## Pins++| Pin | Function |+|---|---|+| 1 | terminal (non-polar) |+| 2 | terminal (non-polar) |++A ceramic capacitor has no polarity: either terminal may face either way (datasheet p.2, "non-polar device").++## Land pattern: KiCad footprint vs KEMET++<table>+<tr>+<td width="104"><a href="land-pattern/README.md"><img src="land-pattern/land-pattern-icon.png" width="112" alt="Land pattern"></a><br><sub> Land pattern </sub></td>+<td>The footprint is KiCad's standard `C_1812_4532Metric`, and this guide lays its pads over KEMET's recommended IPC-7351 land (datasheet p.12, density level B) at true scale. Land centres, length and gap are identical; KiCad's pads are 0.10 mm narrower (3.40 vs 3.50 mm) and have rounded corners. Use it to decide whether to keep the KiCad pads or widen them to KEMET's level B before layout.<br><br><a href="land-pattern/README.md">The comparison, with KEMET's three density levels</a></td>+</tr>+</table>++## 3D model++The model is **KEMET's own STEP** for this part number, downloaded by plain HTTP from KEMET's component documentation+service. KEMET's file (CCS_CCSTD_1812_L4.8W3.5T1.55B0.6) is Y-up with a corner at the origin; `C1812C124J1GACTU.step` is the same+package solid moved by one rigid transform (rotate +90 degrees about X, then translate) so it is Z-up, seated on z = 0 and+centred on the footprint origin, with its face colours copied over and its volume unchanged. KEMET's file also carries a+"KEMET" logo as three 5 um thick solids on top of the ceramic, coloured only with SolidWorks' default lavender. The real+part has no marking (KEMET supplies C0G parts unmarked only, p.15), so the board model leaves the logo out. The download+itself is kept unchanged as `vendor/C1812C124J1GACTU-kemet-original.step`, and every step is recorded in [`provenance/C1812C124J1GACTU.step.json`](provenance/C1812C124J1GACTU.step.json).++The model is drawn at the top of every printed range: 4.80 x 3.50 x 1.55 mm against L 4.50 +/-0.30, W 3.20 +/-0.30 and,+for this part's thickness code GH, T 1.40 +/-0.15 mm. Its terminal band measures 0.88 mm on the top face, inside+B 0.60 +/-0.35 mm. A real part will usually be smaller than the model in all three directions.++The page viewer shows `c1812c124j1gactu-hero.glb`: the clean model plus nonphysical reference artwork drawn under it to the adom-hero+standard (adom/component-hero): the footprint's pads as teal dashed outlines at 50 % opacity, its silkscreen at 70 %+transparency and the pad numbers 1 and 2. The part is non-polar, so no pin-1 dot is added. The artwork never goes into+the STEP, `package-reference.glb` or the board LODs.++++::adom-models{src="/adom/c1812c124j1gactu/render/models.json"}++## Model checked against the printed dimensions++The model was rendered in orthographic top, bottom, side and end views at true scale and laid over a drawing made at the same+scale from the printed limits (nominal outline, tolerance limits, allowed terminal band). Every dimension is inside the printed+range: L 4.800 mm (4.20 to 4.80), W 3.500 mm (2.90 to 3.50), T/H 1.550 mm (1.25 to 1.55), B (band width), top 0.877 mm (0.25 to 0.95), B (band width), bottom 0.877 mm (0.25 to 0.95).++++Source: datasheet C1003_C0G p.3 (1812: L 4.50 +/-0.30, W 3.20 +/-0.30, B 0.60 +/-0.35, S 2.30 min) and p.8 + p.10 (0.12 uF, 100 V: thickness code GH, T 1.40 +/-0.15 mm).++## Board levels of detail++Clean board-use GLBs (no footprint pads, outlines, labels or silkscreen) in four levels, all in the same Z-up, metre,+footprint-origin pose as the STEP. Previews are rendered from each GLB.++::adom-component-lod{src="/adom/c1812c124j1gactu/render/lod/manifest.json"}++## CAD files++| File | What it is |+|---|---|+| `C1812C124J1GACTU.kicad_sym` | KiCad symbol (standard capacitor graphic, pin ends on the 2.54 mm grid) with MPN, Manufacturer, Mouser, DigiKey, LCSC (empty) and Adom Wiki fields |+| `C_1812_4532Metric_C1812C124J1GACTU.kicad_mod` | KiCad footprint (KiCad library `C_1812_4532Metric`, renamed; model `${KIPRJMOD}/C1812C124J1GACTU.step`) |+| `C1812C124J1GACTU.lbr` | Fusion / EAGLE library made with `adom-lbr generate` |+| `altium/C1812C124J1GACTU.SchLib`, `altium/C1812C124J1GACTU.PcbLib` | Altium symbol and footprint libraries (native binary) made with `adom-lbr import-kicad` and `assemble-altium` (the PcbLib embeds the STEP body); `C1812C124J1GACTU.adom-lbr.json` is the adom-lbr hub record |+| `C1812C124J1GACTU.step` | 3D model, STEP: KEMET's package solid, Z-up, seated and centred |+| `vendor/C1812C124J1GACTU-kemet-original.step` | KEMET's STEP exactly as downloaded |+| `package-reference.glb` | 3D model, GLB (clean, for board viewers) |+| `c1812c124j1gactu-hero.glb` | the page's 3D view: package plus footprint pad outlines, silkscreen and pad labels |+| `lod/` | board-use GLBs in four levels of detail, with previews and manifest |++## Datasheet figures++The pages this record cites, cropped from the datasheet:++| Figure | Source |+|---|---|+| [p.1 overview (no change in capacitance with time and voltage, +/-30 ppm/C) and ordering information (C 1812 C 124 J 1 G A C TU)](docs/figures/kemet-ds-p1-overview-ordering.png) | KEMET C1003_C0G, p.1 |+| [p.2 packaging C-spec (TU = 7 inch reel, unmarked) and benefits (no capacitance change with applied rated DC voltage, no decay with time)](docs/figures/kemet-ds-p2-benefits-packaging.png) | KEMET C1003_C0G, p.2 |+| [p.3 dimensions: 1812 L 4.50 +/-0.30, W 3.20 +/-0.30, B 0.60 +/-0.35, S 2.30 min (mm)](docs/figures/kemet-ds-p3-dimensions.png) | KEMET C1003_C0G, p.3 |+| [p.4 electrical parameters: -55 to +125 C, +/-30 ppm/C, 0 % aging, DWV 250 %, DF 0.1 %, IR](docs/figures/kemet-ds-p4-electrical.png) | KEMET C1003_C0G, p.4 |+| [p.8 Table 1B: 0.12 uF (124) in C1812C at 100 V (voltage code 1) has chip thickness code GH](docs/figures/kemet-ds-p8-waterfall-1812.png) | KEMET C1003_C0G, p.8 |+| [p.10 Table 2A: thickness code GH = 1.40 +/-0.15 mm; 1,000 pcs per 7 inch plastic reel](docs/figures/kemet-ds-p10-thickness.png) | KEMET C1003_C0G, p.10 |+| [p.12 Table 3: IPC-7351 land pattern for 1812 at density levels A, B and C](docs/figures/kemet-ds-p12-land-pattern.png) | KEMET C1003_C0G, p.12 |+| [p.13 soldering: reflow only for 1812, profile for 100 % matte Sn (260 C peak)](docs/figures/kemet-ds-p13-soldering.png) | KEMET C1003_C0G, p.13 |+| [p.15 construction and marking: C0G devices are supplied unmarked only](docs/figures/kemet-ds-p15-marking.png) | KEMET C1003_C0G, p.15 |++## Sources and license++- KEMET datasheet C1003_C0G, 2/20/2025 (https://content.kemet.com/datasheets/KEM_C1003_C0G_SMD.pdf), sha256 02d179914aeb9585eb2229ba8e18ef9d6b01c77c056de2af295d6950a2a5cc0d+- KEMET 3D model: https://search.kemet.com/component-documentation/download/step/C1812C124J1GACTU.step, sha256 b5d45febdee8defce1c3da229b540ed0a72760aeaa02501c728f7f8143eb6de7, 2026-10-21+- KiCad library footprint: [Capacitor_SMD.pretty/C_1812_4532Metric.kicad_mod](https://gitlab.com/kicad/libraries/kicad-footprints/-/blob/master/Capacitor_SMD.pretty/C_1812_4532Metric.kicad_mod)+- Distributor numbers, stock and prices: Mouser, DigiKey and JLCPCB/LCSC through the Adom parts search, 2026-10-21++Original Adom content is CC-BY-4.0. KEMET's STEP, its derivatives and the datasheet keep KEMET's terms and the KiCad+footprint keeps its upstream license (CC-BY-SA 4.0 with the KiCad library exception); see [LICENSE](LICENSE).+[provenance.json](provenance.json) records every source and file hash; the scripts that built the checks are in+`provenance/tools/`.++This is a catalog record for the part, not a manufacturing approval: check KEMET's current specification for your design.
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c1812c124j1gactu-hero.overlay.jsonadded+125@@ -0,0 +1,125 @@+{+ "spec": "adom-hero 1.4",+ "mpn": "C1812C124J1GACTU",+ "kind": "component + footprint reference art",+ "board_use": false,+ "plane_z_mm": -0.02,+ "units": "metre",+ "upAxis": "Z",+ "layers": {+ "pad_outlines": {+ "material": "Footprint pads - teal dashed outlines - 50 percent opacity",+ "rgba": [+ 0.0,+ 0.902,+ 0.863,+ 0.5+ ],+ "pads": 2,+ "span_mm": 5.5,+ "dash_mm": 0.1375,+ "gap_mm": 0.0825,+ "pad_stroke_mm": 0.033+ },+ "silkscreen": {+ "material": "Silkscreen reference lines - 30 percent opacity",+ "rgba": [+ 0.92,+ 0.96,+ 1.0,+ 0.3+ ],+ "footprint_items": 2,+ "pin1": null+ },+ "signal_names": {+ "material": "Signal names - 50 percent opacity",+ "rgba": [+ 0.92,+ 0.96,+ 1.0,+ 0.5+ ],+ "font": "DejaVu Sans Mono",+ "labels": 2,+ "sides": "top + mirrored underside (single-sided)",+ "omitted": null,+ "fallback_to_pad_number": 2+ }+ },+ "align": {+ "ok": true,+ "centre_offset_mm": 0.0,+ "tolerance_mm": 0.44,+ "orientation_flipped": false,+ "contacts_bbox_mm": [+ -2.4,+ 2.4,+ -1.75,+ 1.75+ ],+ "pads_bbox_mm": [+ -2.75,+ 2.75,+ -1.7,+ 1.7+ ],+ "seating_z_mm": 0.0+ },+ "sources": {+ "glb": "package-reference.glb",+ "glb_sha256": "53804863334397774437d2712467f7d99cf6a28381b8ca78c498bbbfedcf5aa2",+ "footprint": "C_1812_4532Metric_C1812C124J1GACTU.kicad_mod",+ "footprint_sha256": "3a3d40605d16f4d89e01f0719afb667d0669a0b53ec5e4bad052f8eafab3a29d",+ "pins": "page.json component.pins"+ },+ "generator": "factory/hero_glb.py",+ "labels": [+ {+ "pad": "1",+ "text": "1",+ "x": -2.9,+ "y": 0.0,+ "align": "right",+ "vertical": false,+ "h": 0.6+ },+ {+ "pad": "2",+ "text": "2",+ "x": 2.9,+ "y": 0.0,+ "align": "left",+ "vertical": false,+ "h": 0.6+ }+ ],+ "pads": [+ {+ "number": "1",+ "shape": "roundrect",+ "center_mm": [+ -2.05,+ 0.0+ ],+ "size_mm": [+ 1.4,+ 3.4+ ],+ "rot": 0.0+ },+ {+ "number": "2",+ "shape": "roundrect",+ "center_mm": [+ 2.05,+ 0.0+ ],+ "size_mm": [+ 1.4,+ 3.4+ ],+ "rot": 0.0+ }+ ]+}
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docs/figures/figures.jsonadded+119@@ -0,0 +1,119 @@+[+ {+ "file": "docs/figures/kemet-ds-p1-overview-ordering.png",+ "document": "KEMET, Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs), C0G Dielectric, 10 to 250 VDC (Commercial Grade), C1003_C0G, 2/20/2025 (22 pages)",+ "page": 1,+ "crop_px_at_150dpi": [+ 60,+ 180,+ 1215,+ 1515+ ],+ "caption": "p.1 overview (no change in capacitance with time and voltage, +/-30 ppm/C) and ordering information (C 1812 C 124 J 1 G A C TU)",+ "sha256": "b24fcc4cfcf3ee41c7a2a3fcc681658b12e9bec39249a544b4d5e95967b935f0"+ },+ {+ "file": "docs/figures/kemet-ds-p2-benefits-packaging.png",+ "document": "KEMET, Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs), C0G Dielectric, 10 to 250 VDC (Commercial Grade), C1003_C0G, 2/20/2025 (22 pages)",+ "page": 2,+ "crop_px_at_150dpi": [+ 60,+ 150,+ 1215,+ 810+ ],+ "caption": "p.2 packaging C-spec (TU = 7 inch reel, unmarked) and benefits (no capacitance change with applied rated DC voltage, no decay with time)",+ "sha256": "66fc63e1866b22ed7f1d358d9a1c40f1bbc5d8ad848afd1050926927df1b4689"+ },+ {+ "file": "docs/figures/kemet-ds-p3-dimensions.png",+ "document": "KEMET, Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs), C0G Dielectric, 10 to 250 VDC (Commercial Grade), C1003_C0G, 2/20/2025 (22 pages)",+ "page": 3,+ "crop_px_at_150dpi": [+ 60,+ 150,+ 1215,+ 1185+ ],+ "caption": "p.3 dimensions: 1812 L 4.50 +/-0.30, W 3.20 +/-0.30, B 0.60 +/-0.35, S 2.30 min (mm)",+ "sha256": "4ca075141bbbf7977223b2d8b9aa1f377722b5d1fe7a1bd77ca96d311743b1d9"+ },+ {+ "file": "docs/figures/kemet-ds-p4-electrical.png",+ "document": "KEMET, Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs), C0G Dielectric, 10 to 250 VDC (Commercial Grade), C1003_C0G, 2/20/2025 (22 pages)",+ "page": 4,+ "crop_px_at_150dpi": [+ 60,+ 150,+ 1215,+ 1035+ ],+ "caption": "p.4 electrical parameters: -55 to +125 C, +/-30 ppm/C, 0 % aging, DWV 250 %, DF 0.1 %, IR",+ "sha256": "bf8972f6aa1ad36e02fd95f6c1e77fe98055ead639904713c4e03a46227c3f7b"+ },+ {+ "file": "docs/figures/kemet-ds-p8-waterfall-1812.png",+ "document": "KEMET, Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs), C0G Dielectric, 10 to 250 VDC (Commercial Grade), C1003_C0G, 2/20/2025 (22 pages)",+ "page": 8,+ "crop_px_at_150dpi": [+ 60,+ 150,+ 1215,+ 1080+ ],+ "caption": "p.8 Table 1B: 0.12 uF (124) in C1812C at 100 V (voltage code 1) has chip thickness code GH",+ "sha256": "b558affcc15fd4dc980a348155b4f2217d6dc4a26d8151121f1a4e0b156a9b39"+ },+ {+ "file": "docs/figures/kemet-ds-p10-thickness.png",+ "document": "KEMET, Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs), C0G Dielectric, 10 to 250 VDC (Commercial Grade), C1003_C0G, 2/20/2025 (22 pages)",+ "page": 10,+ "crop_px_at_150dpi": [+ 60,+ 150,+ 915,+ 1440+ ],+ "caption": "p.10 Table 2A: thickness code GH = 1.40 +/-0.15 mm; 1,000 pcs per 7 inch plastic reel",+ "sha256": "7211050566dcb2acafd592c9491b533f7c6c894bf6fbacecd2631484d3bd25e3"+ },+ {+ "file": "docs/figures/kemet-ds-p12-land-pattern.png",+ "document": "KEMET, Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs), C0G Dielectric, 10 to 250 VDC (Commercial Grade), C1003_C0G, 2/20/2025 (22 pages)",+ "page": 12,+ "crop_px_at_150dpi": [+ 60,+ 150,+ 1215,+ 1350+ ],+ "caption": "p.12 Table 3: IPC-7351 land pattern for 1812 at density levels A, B and C",+ "sha256": "c6245d9166539a8b215114c2364e169762830081943bd3258e8ee1974288b821"+ },+ {+ "file": "docs/figures/kemet-ds-p13-soldering.png",+ "document": "KEMET, Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs), C0G Dielectric, 10 to 250 VDC (Commercial Grade), C1003_C0G, 2/20/2025 (22 pages)",+ "page": 13,+ "crop_px_at_150dpi": [+ 60,+ 150,+ 1215,+ 1095+ ],+ "caption": "p.13 soldering: reflow only for 1812, profile for 100 % matte Sn (260 C peak)",+ "sha256": "3c337c99956fb0ba4e6ed1d7acaa5671618b2b59d1b793764926fc69f6442db7"+ },+ {+ "file": "docs/figures/kemet-ds-p15-marking.png",+ "document": "KEMET, Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs), C0G Dielectric, 10 to 250 VDC (Commercial Grade), C1003_C0G, 2/20/2025 (22 pages)",+ "page": 15,+ "crop_px_at_150dpi": [+ 60,+ 150,+ 1215,+ 1170+ ],+ "caption": "p.15 construction and marking: C0G devices are supplied unmarked only",+ "sha256": "0af48889b2a288a2fe612c5f01403017b43105619b7e2acc11406be113083466"+ }+]
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