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br25g256fj-3ge2: factory component page (tier=lcsc)

Ray ·fa300c4fc9 ·2mo ago ·parent 01276d0
1 file changed +116−8
page.json+116−8
@@ -1,13 +1,126 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "br25g256fj-3ge2",+  "title": "BR25G256FJ-3GE2",+  "brief": "ROHM EEPROM, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",-  "type": "component",-  "description": "ROHM EEPROM, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "memory",     "br25g256fj-3ge2"   ],+  "component": {+    "mpn": "BR25G256FJ-3GE2",+    "manufacturer": "ROHM",+    "package": "SOIC-8",+    "pin_count": 8,+    "category": "Memory",+    "subcategory": "EEPROM",+    "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2211030200_ROHM-Semicon-BR25G256FJ-3GE2_C509766.pdf",+    "parts": {+      "symbol": "br25g256fj-3ge2.kicad_sym",+      "footprint": "br25g256fj-3ge2.kicad_mod",+      "model_3d": "br25g256fj-3ge2.glb",+      "model_3d_step": "br25g256fj-3ge2.step",+      "lbr": "br25g256fj-3ge2.lbr"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "CSB",+        "type": "input",+        "description": "Active-low chip select input. Drive low to select the device and frame an SPI transaction; drive high to deselect and place SO in high impedance. Referenced to Vcc; VIH >= 0.7*Vcc (>=0.8*Vcc below 1.7V)."+      },+      {+        "number": "2",+        "name": "SO",+        "type": "output",+        "description": "Serial data output (MISO). Data is shifted out MSB first on the falling edge of SCK. High-impedance when CSB is high or HOLDB is asserted. Drive strength: VOH >= Vcc-0.2 V at IOH = -2 mA (2.5-5.5 V)."+      },+      {+        "number": "3",+        "name": "WPB",+        "type": "input",+        "description": "Active-low hardware write-protect input. When low, the WRSR (Write Status Register) command is inhibited, locking the block-protection bits BP0/BP1 and preventing changes to write protection."+      },+      {+        "number": "4",+        "name": "GND",+        "type": "power_in",+        "description": "Ground reference (0 V) for all inputs, outputs, and internal circuitry."+      },+      {+        "number": "5",+        "name": "SI",+        "type": "input",+        "description": "Serial data input (MOSI). Op-code, address, and write data are shifted in MSB first on the rising edge of SCK. Setup time tDIS = 5 ns min at Vcc >= 4.5 V."+      },+      {+        "number": "6",+        "name": "SCK",+        "type": "input",+        "description": "Serial clock input. Supports SPI modes (CPOL,CPHA) = (0,0) and (1,1) up to 20 MHz max at Vcc >= 4.5 V (5 MHz max at 1.7-2.5 V, 3 MHz max at 1.6-1.7 V)."+      },+      {+        "number": "7",+        "name": "HOLDB",+        "type": "input",+        "description": "Active-low hold input. Pulling HOLDB low while CSB is low pauses the current SPI transaction and forces SO to high impedance; the transaction resumes when HOLDB returns high. Allows the master to service higher-priority devices on a shared bus."+      },+      {+        "number": "8",+        "name": "Vcc",+        "type": "power_in",+        "description": "Positive supply, 1.6 V to 5.5 V. Recommended bypass capacitor 0.1 uF to GND. Typical read current 0.1 uA standby, 2.0 mA read, 0.6 mA write at 5 V."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2211030200_ROHM-Semicon-BR25G256FJ-3GE2_C509766.pdf",+        "pages": 37,+        "sha256": "6e0b88fc30c2ef44",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 8,+        "described": 8,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Manufacturer": "ROHM",+      "Package": "SOIC-8",+      "Category": "Memory",+      "Pins": "8"+    }+  },+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "br25g256fj-3ge2"+  ],+  "discovery_pitch": "BR25G256FJ-3GE2 (ROHM) component page with datasheet-verified CAD.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -25,10 +138,5 @@     "docs/br25g256fj-3ge2-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file