component
BQ76PL102RGTR
Public Made by Adomby adom
Texas Instruments Battery Management, VQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+53@@ -0,0 +1,53 @@+# BQ76PL102RGTR++**Texas Instruments** · Battery Management · VQFN-16-EP(3x3)++BQ76PL102RGTR from Texas Instruments, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VSS | power_in | Connect to the most-negative cell voltage (cell 1 negative) of the series string. |+| 2 | VLDO | power_out | Low-dropout regulator output that must be connected to VPP and bypassed with a 4.7 µF capacitor. |+| 3 | TDI | unconnected | Do not connect. |+| 4 | SDI | input | PowerLAN serial data input from the lower (south, downstream) part, capacitively coupled, with rise and fall times limited to 500 ns. |+| 5 | PUMP1S | output | Charge-balance gate drive for cell 1 south, switching the cell-balancing MOSFET that pumps charge to the next lower cell. |+| 6 | PUMP1N | output | Charge-balance gate drive for cell 1 north, switching the cell-balancing MOSFET that pumps charge from cell 1 to cell 2. |+| 7 | PUMP2S | output | Charge-balance gate drive for cell 2 south, switching the cell-balancing MOSFET that pumps charge from cell 2 to cell 1. |+| 8 | PUMP2N | output | Charge-balance gate drive for cell 2 north, switching the cell-balancing MOSFET that pumps charge to the next higher cell. |+| 9 | SDO | output | PowerLAN serial data output to the north (upstream) part, capacitively coupled with output logic high of 0.9 VLDO minimum. |+| 10 | TCK | unconnected | Do not connect. |+| 11 | TMD | unconnected | Do not connect. |+| 12 | V2 | power_in | Connect to the most-positive cell voltage (cell 2 positive); also an analog input for cell 2 voltage measurement, and to V1 of the topmost device when the stack has an odd number of cells. |+| 13 | XT2 | input | External temperature sensor 2 analog input, using a calibrated 50 µA sensor current. |+| 14 | XT1 | input | External temperature sensor 1 analog input, using a calibrated 50 µA sensor current. |+| 15 | V1 | input | Midpoint cell connection (cell 1 positive and cell 2 negative) used as an analog input for cell voltage measurement. |+| 16 | VPP | power_in | Connect to VLDO, the low-dropout regulator output. |+| 17 | Thermal pad | power_in | Exposed thermal pad that must be connected to VSS and soldered to the PCB for thermal and mechanical performance. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-16-EP(3x3) |+| Category | Power Management (PMIC) |+| Pins | 17 |++## CAD (KiCad official)++- Symbol: `BQ76PL102RGTR`+- Footprint: `Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm`+- 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)+- 3D model files: `bq76pl102rgtr-etched.step` / `bq76pl102rgtr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `bq76pl102rgtr.step` / `bq76pl102rgtr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/bq76pl102.pdf) (22 pp, sha256 `fe8ff75e3d430c51`, retrieved 2026-10-07, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/bq76pl102rgtr-datasheet.pdf)
page.jsonadded+255@@ -0,0 +1,255 @@+{+ "slug": "bq76pl102rgtr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Battery Management, VQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "bq76pl102rgtr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "bq76pl102rgtr.kicad_sym",+ "bq76pl102rgtr.kicad_mod",+ "bq76pl102rgtr.glb",+ "bq76pl102rgtr.step",+ "bq76pl102rgtr.lbr",+ "docs/hero.png",+ "docs/bq76pl102rgtr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "bq76pl102rgtr-hero.glb",+ "bq76pl102rgtr-hero.overlay.json"+ ],+ "component": {+ "mpn": "BQ76PL102RGTR",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-16-EP(3x3)",+ "pin_count": 17,+ "category": "Power Management (PMIC)",+ "subcategory": "Battery Management",+ "datasheet": "https://www.ti.com/lit/ds/symlink/bq76pl102.pdf",+ "parts": {+ "symbol": "bq76pl102rgtr.kicad_sym",+ "footprint": "bq76pl102rgtr.kicad_mod",+ "model_3d": "bq76pl102rgtr-hero.glb",+ "model_3d_plain": "bq76pl102rgtr.glb",+ "model_3d_step": "bq76pl102rgtr-etched.step",+ "model_3d_step_plain": "bq76pl102rgtr.step",+ "lbr": "bq76pl102rgtr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2866695",+ "digikey": "296-27731-2-ND",+ "mouser": "595-BQ76PL102RGTR"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T22:44:37Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-27731-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-BQ76PL102RGTR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "VSS",+ "type": "power_in",+ "description": "Connect to the most-negative cell voltage (cell 1 negative) of the series string."+ },+ {+ "number": "2",+ "name": "VLDO",+ "type": "power_out",+ "description": "Low-dropout regulator output that must be connected to VPP and bypassed with a 4.7 µF capacitor."+ },+ {+ "number": "3",+ "name": "TDI",+ "type": "unconnected",+ "description": "Do not connect."+ },+ {+ "number": "4",+ "name": "SDI",+ "type": "input",+ "description": "PowerLAN serial data input from the lower (south, downstream) part, capacitively coupled, with rise and fall times limited to 500 ns."+ },+ {+ "number": "5",+ "name": "PUMP1S",+ "type": "output",+ "description": "Charge-balance gate drive for cell 1 south, switching the cell-balancing MOSFET that pumps charge to the next lower cell."+ },+ {+ "number": "6",+ "name": "PUMP1N",+ "type": "output",+ "description": "Charge-balance gate drive for cell 1 north, switching the cell-balancing MOSFET that pumps charge from cell 1 to cell 2."+ },+ {+ "number": "7",+ "name": "PUMP2S",+ "type": "output",+ "description": "Charge-balance gate drive for cell 2 south, switching the cell-balancing MOSFET that pumps charge from cell 2 to cell 1."+ },+ {+ "number": "8",+ "name": "PUMP2N",+ "type": "output",+ "description": "Charge-balance gate drive for cell 2 north, switching the cell-balancing MOSFET that pumps charge to the next higher cell."+ },+ {+ "number": "9",+ "name": "SDO",+ "type": "output",+ "description": "PowerLAN serial data output to the north (upstream) part, capacitively coupled with output logic high of 0.9 VLDO minimum."+ },+ {+ "number": "10",+ "name": "TCK",+ "type": "unconnected",+ "description": "Do not connect."+ },+ {+ "number": "11",+ "name": "TMD",+ "type": "unconnected",+ "description": "Do not connect."+ },+ {+ "number": "12",+ "name": "V2",+ "type": "power_in",+ "description": "Connect to the most-positive cell voltage (cell 2 positive); also an analog input for cell 2 voltage measurement, and to V1 of the topmost device when the stack has an odd number of cells."+ },+ {+ "number": "13",+ "name": "XT2",+ "type": "input",+ "description": "External temperature sensor 2 analog input, using a calibrated 50 µA sensor current."+ },+ {+ "number": "14",+ "name": "XT1",+ "type": "input",+ "description": "External temperature sensor 1 analog input, using a calibrated 50 µA sensor current."+ },+ {+ "number": "15",+ "name": "V1",+ "type": "input",+ "description": "Midpoint cell connection (cell 1 positive and cell 2 negative) used as an analog input for cell voltage measurement."+ },+ {+ "number": "16",+ "name": "VPP",+ "type": "power_in",+ "description": "Connect to VLDO, the low-dropout regulator output."+ },+ {+ "number": "17",+ "name": "Thermal pad",+ "type": "power_in",+ "description": "Exposed thermal pad that must be connected to VSS and soldered to the PCB for thermal and mechanical performance."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet pin table (page 4) lists the thermal pad with no pin number ('—'). The number 17 is ta; TDI (3), TCK (10) and TMD (11) are marked NC, 'Do not connect', in the pin table, so they are typed ; V2 is marked 'P, IA' and V1 'IA' in the pin table. V2 is typed power_in and V1 input, since the data",+ "1/17 pins cited to the wrong page (name found elsewhere): ['17:Thermal pad@p4']"+ ],+ "pages_sent": 22,+ "cost_usd": 0.101,+ "at": "2026-10-07T22:44:22"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/bq76pl102.pdf",+ "pages": 22,+ "sha256": "fe8ff75e3d430c51",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 17,+ "described": 17,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "bq76pl102rgtr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 3,+ 3,+ 0.785+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3eb81ffac423a66cdcfead8efe56401da171edaf1f2257049aad7b2d3900f6c8",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "bq76pl102rgtr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 3,+ 3,+ 0.785+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "b8d3980bfc9044d3665a11aeeba6502872d165a93964e0a5bf7c7efed45d05ae",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}