component
BQ76942PFBR
Public Made by Adomby adom
Texas Instruments Battery Management, TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+85@@ -0,0 +1,85 @@+# BQ76942PFBR++**Texas Instruments** · Battery Management · TQFP-48(7x7)++BQ76942PFBR from Texas Instruments, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | NC | unconnected | This pin is not connected to silicon. |+| 2 | VC9 | input | Ninth cell sense voltage input, VSS-0.3 to VSS+85 V relative to VC8. |+| 3 | NC | unconnected | This pin is not connected to silicon. |+| 4 | VC8 | input | Eighth cell sense voltage input, VSS-0.3 to VSS+85 V relative to VC7. |+| 5 | NC | unconnected | This pin is not connected to silicon. |+| 6 | VC7 | input | Seventh cell sense voltage input, VSS-0.3 to VSS+85 V relative to VC6. |+| 7 | NC | unconnected | This pin is not connected to silicon. |+| 8 | VC6 | input | Sixth cell sense voltage input, VSS-0.3 to VSS+85 V relative to VC5. |+| 9 | NC | unconnected | This pin is not connected to silicon. |+| 10 | VC5 | input | Fifth cell sense voltage input, VSS-0.3 to VSS+85 V relative to VC4. |+| 11 | NC | unconnected | This pin is not connected to silicon. |+| 12 | VC4 | input | Fourth cell sense voltage input, VSS-0.3 to VSS+85 V relative to VC3. |+| 13 | VC3 | input | Third cell sense voltage input, VSS-0.3 to VSS+85 V relative to VC2. |+| 14 | VC2 | input | Second cell sense voltage input, VSS-0.3 to VSS+85 V relative to VC1. |+| 15 | VC1 | input | First cell sense voltage input, VSS-0.3 to VSS+85 V relative to VC0. |+| 16 | VC0 | input | First cell negative terminal voltage input, VSS-0.3 to VSS+6 V. |+| 17 | VSS | power_in | Device ground connection. |+| 18 | SRP | input | Coulomb counter sense resistor top input, VSS-0.3 to VREG18 + 0.3 V during operation. |+| 19 | NC | unconnected | This pin is not connected to silicon. |+| 20 | SRN | input | Coulomb counter sense resistor bottom input, VSS-0.3 to VREG18 + 0.3 V during operation. |+| 21 | TS1 | bidirectional | Thermistor or general purpose ADC input, accepting VSS-0.2 to VREG18 + 0.3 V. |+| 22 | TS2 | bidirectional | Thermistor or ADC input and SHUTDOWN mode wakeup pin, accepting VSS-0.2 to VREG18 + 0.3 V, with weak pulldown to VSS in SHUTDOWN. |+| 23 | TS3 | bidirectional | Thermistor or general purpose ADC input, accepting VSS-0.2 to VREG18 + 0.3 V. |+| 24 | REG18 | power_out | Internal 1.8 V LDO output regulated to 1.6 to 2.0 V, providing 3 to 14 mA short-circuit current limit for internal use. |+| 25 | ALERT | bidirectional | Multifunction pin for alarm interrupt, HDQ interface, thermistor, or digital I/O (VSS-0.3 to VSS+6 V, or VSS-0.2 to VREG18 + 0.3 V for ADC/thermistor). |+| 26 | SCL | bidirectional | I2C clock or SPI serial clock with open-drain output, VSS-0.3 to VSS+6 V, supporting 400 kHz I2C mode. |+| 27 | SDA | bidirectional | I2C data or SPI MISO with open-drain for I2C or active drive for SPI, VSS-0.3 to VSS+6 V, supporting 400 kHz I2C mode. |+| 28 | HDQ | bidirectional | Multifunction pin for HDQ single-wire, SPI MOSI, thermistor, or digital I/O (VSS-0.3 to VSS+6 V, or VSS-0.2 to VREG18 + 0.3 V for ADC/thermistor). |+| 29 | CFETOFF | bidirectional | Charge FET disable input (low disables CHG/PCHG), SPI chip select, thermistor, or digital I/O (VSS-0.3 to VSS+6 V, or VSS-0.2 to VREG18 + 0.3 V for ADC/thermistor). |+| 30 | DFETOFF | bidirectional | Discharge FET disable input (low disables DSG/PDSG or both in BOTHOFF mode), thermistor, or digital I/O (VSS-0.3 to VSS+6 V, or VSS-0.2 to VREG18 + 0.3 V for ADC/thermistor). |+| 31 | DCHG | bidirectional | Charge FET fault status open-drain output or thermistor/digital I/O (VSS-0.3 to VSS+6 V, or VSS-0.2 to VREG18 + 0.3 V for ADC/thermistor). |+| 32 | DDSG | bidirectional | Discharge FET fault status open-drain output or thermistor/digital I/O (VSS-0.3 to VSS+6 V, or VSS-0.2 to VREG18 + 0.3 V for ADC/thermistor). |+| 33 | RST_SHUT | input | Reset or shutdown digital input, VSS-0.3 to VSS+6 V logic level, with >1 second assertion triggering SHUTDOWN mode. |+| 34 | REG2 | power_out | Second programmable LDO output (1.8 V / 2.5 V / 3.0 V / 3.3 V / 5.0 V selectable), providing up to 45 mA with 47 to 80 mA short-circuit current limit. |+| 35 | REG1 | power_out | First programmable LDO output (1.8 V / 2.5 V / 3.0 V / 3.3 V / 5.0 V selectable), providing up to 45 mA with 47 to 80 mA short-circuit current limit. |+| 36 | REGIN | input | LDO supply input providing ~5.5 V from internal pre-regulator or external source for REG1 and REG2, with voltage range maximum of VSS-0.3 or VBREG-5.5 to minimum of VSS+6 or VBAT+0.3. |+| 37 | BREG | output | Pre-regulator base drive for external NPN BJT, maximum output current 2.5 to 3.33 mA at short circuit. |+| 38 | FUSE | bidirectional | Fuse drive output (VSS-0.3 to minimum of VSS+20 or VBAT+0.3 V) and secondary protector sense input (VSS-0.3 to VSS+6 V with maximum 2 mA current limit). |+| 39 | PDSG | output | Predischarge PFET gate control output, voltage approximately VBAT to VBAT-0.5 V depending on supply level. |+| 40 | PCHG | output | Precharge PFET gate control output, voltage approximately VPACK to VPACK-0.5 V depending on supply level. |+| 41 | LD | bidirectional | Load detect pin for pack removal sensing (VSS-0.3 to VSS+85 V) or current source output in SHUTDOWN mode, with internal pullup current 35 to 172 µA. |+| 42 | PACK | input | PACK+ voltage sense input measuring top-of-stack after protection FETs, VSS-0.3 to VSS+85 V, with ±0.5 V measurement accuracy after calibration. |+| 43 | DSG | output | Discharge NFET gate drive output, VSS-0.3 to VSS+85 V range, gate-source voltage 4.5 to 7 V (low overdrive) or 10 to 13 V (high overdrive) relative to BAT. |+| 44 | NC | unconnected | This pin is not connected to silicon. |+| 45 | CHG | output | Charge NFET gate drive output, VSS-0.3 to VSS+85 V range, gate-source voltage 4.5 to 7 V (low overdrive) or 10 to 13 V (high overdrive) relative to BAT. |+| 46 | CP1 | bidirectional | Charge pump external capacitor connection (100 to 2200 nF recommended), voltage range VBAT-0.3 to minimum of VSS+85 or VBAT+15 V. |+| 47 | BAT | power_in | Primary power supply input from battery stack top through series diode, VSS-0.3 to VSS+85 V absolute maximum, typical 4.7 to 55 V operating range. |+| 48 | VC10 | input | Tenth cell top-of-stack sense voltage input, measuring between maximum of VSS-0.3 and VC9-0.3 to VSS+85 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TQFP-48(7x7) |+| Category | Power Management (PMIC) |+| Pins | 48 |++## CAD (KiCad official)++- Symbol: `BQ76942PFBR`+- Footprint: `Package_QFP:TQFP-48_7x7mm_P0.5mm`+- 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)+- 3D model files: `bq76942pfbr-etched.step` / `bq76942pfbr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `bq76942pfbr.step` / `bq76942pfbr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/bq76942) (85 pp, sha256 `a976a88e92abb957`, retrieved 2026-09-23, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/bq76942pfbr-datasheet.pdf)
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Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "bq76942pfbr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "bq76942pfbr.kicad_sym",+ "bq76942pfbr.kicad_mod",+ "bq76942pfbr.glb",+ "bq76942pfbr.step",+ "bq76942pfbr.lbr",+ "docs/hero.png",+ "docs/bq76942pfbr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "BQ76942PFBR",+ "manufacturer": "Texas Instruments",+ "package": "TQFP-48(7x7)",+ "pin_count": 48,+ "category": "Power Management (PMIC)",+ "subcategory": "Battery Management",+ "datasheet": "https://www.ti.com/cn/lit/gpn/bq76942",+ "parts": {+ "symbol": "bq76942pfbr.kicad_sym",+ "footprint": "bq76942pfbr.kicad_mod",+ "model_3d": "bq76942pfbr-etched.glb",+ "model_3d_plain": "bq76942pfbr.glb",+ "model_3d_step": "bq76942pfbr-etched.step",+ "model_3d_step_plain": "bq76942pfbr.step",+ "lbr": "bq76942pfbr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2692351"+ },+ "pins": [+ {+ "number": "1",+ "name": "NC",+ "type": "unconnected",+ "description": "This pin is not connected to silicon."+ },+ {+ "number": "2",+ "name": "VC9",+ "type": "input",+ "description": "Ninth cell sense voltage input, VSS-0.3 to VSS+85 V relative to VC8."+ },+ {+ "number": "3",+ "name": "NC",+ "type": "unconnected",+ "description": "This pin is not connected to silicon."+ },+ {+ "number": "4",+ "name": "VC8",+ "type": "input",+ "description": "Eighth cell sense voltage input, VSS-0.3 to VSS+85 V relative to VC7."+ },+ {+ "number": "5",+ "name": "NC",+ "type": "unconnected",+ "description": "This pin is not connected to silicon."+ },+ {+ "number": "6",+ "name": "VC7",+ "type": "input",+ "description": "Seventh cell sense voltage input, VSS-0.3 to VSS+85 V relative to VC6."+ },+ {+ "number": "7",+ "name": "NC",+ "type": "unconnected",+ "description": "This pin is not connected to silicon."+ },+ {+ "number": "8",+ "name": "VC6",+ "type": "input",+ "description": "Sixth cell sense voltage input, VSS-0.3 to VSS+85 V relative to VC5."+ },+ {+ "number": "9",+ "name": "NC",+ "type": "unconnected",+ "description": "This pin is not connected to silicon."+ },+ {+ "number": "10",+ "name": "VC5",+ "type": "input",+ "description": "Fifth cell sense voltage input, VSS-0.3 to VSS+85 V relative to VC4."+ },+ {+ "number": "11",+ "name": "NC",+ "type": "unconnected",+ "description": "This pin is not connected to silicon."+ },+ {+ "number": "12",+ "name": "VC4",+ "type": "input",+ "description": "Fourth cell sense voltage input, VSS-0.3 to VSS+85 V relative to VC3."+ },+ {+ "number": "13",+ "name": "VC3",+ "type": "input",+ "description": "Third cell sense voltage input, VSS-0.3 to VSS+85 V relative to VC2."+ },+ {+ "number": "14",+ "name": "VC2",+ "type": "input",+ "description": "Second cell sense voltage input, VSS-0.3 to VSS+85 V relative to VC1."+ },+ {+ "number": "15",+ "name": "VC1",+ "type": "input",+ "description": "First cell sense voltage input, VSS-0.3 to VSS+85 V relative to VC0."+ },+ {+ "number": "16",+ "name": "VC0",+ "type": "input",+ "description": "First cell negative terminal voltage input, VSS-0.3 to VSS+6 V."+ },+ {+ "number": "17",+ "name": "VSS",+ "type": "power_in",+ "description": "Device ground connection."+ },+ {+ "number": "18",+ "name": "SRP",+ "type": "input",+ "description": "Coulomb counter sense resistor top input, VSS-0.3 to VREG18 + 0.3 V during operation."+ },+ {+ "number": "19",+ "name": "NC",+ "type": "unconnected",+ "description": "This pin is not connected to silicon."+ },+ {+ "number": "20",+ "name": "SRN",+ "type": "input",+ "description": "Coulomb counter sense resistor bottom input, VSS-0.3 to VREG18 + 0.3 V during operation."+ },+ {+ "number": "21",+ "name": "TS1",+ "type": "bidirectional",+ "description": "Thermistor or general purpose ADC input, accepting VSS-0.2 to VREG18 + 0.3 V."+ },+ {+ "number": "22",+ "name": "TS2",+ "type": "bidirectional",+ "description": "Thermistor or ADC input and SHUTDOWN mode wakeup pin, accepting VSS-0.2 to VREG18 + 0.3 V, with weak pulldown to VSS in SHUTDOWN."+ },+ {+ "number": "23",+ "name": "TS3",+ "type": "bidirectional",+ "description": "Thermistor or general purpose ADC input, accepting VSS-0.2 to VREG18 + 0.3 V."+ },+ {+ "number": "24",+ "name": "REG18",+ "type": "power_out",+ "description": "Internal 1.8 V LDO output regulated to 1.6 to 2.0 V, providing 3 to 14 mA short-circuit current limit for internal use."+ },+ {+ "number": "25",+ "name": "ALERT",+ "type": "bidirectional",+ "description": "Multifunction pin for alarm interrupt, HDQ interface, thermistor, or digital I/O (VSS-0.3 to VSS+6 V, or VSS-0.2 to VREG18 + 0.3 V for ADC/thermistor)."+ },+ {+ "number": "26",+ "name": "SCL",+ "type": "bidirectional",+ "description": "I2C clock or SPI serial clock with open-drain output, VSS-0.3 to VSS+6 V, supporting 400 kHz I2C mode."+ },+ {+ "number": "27",+ "name": "SDA",+ "type": "bidirectional",+ "description": "I2C data or SPI MISO with open-drain for I2C or active drive for SPI, VSS-0.3 to VSS+6 V, supporting 400 kHz I2C mode."+ },+ {+ "number": "28",+ "name": "HDQ",+ "type": "bidirectional",+ "description": "Multifunction pin for HDQ single-wire, SPI MOSI, thermistor, or digital I/O (VSS-0.3 to VSS+6 V, or VSS-0.2 to VREG18 + 0.3 V for ADC/thermistor)."+ },+ {+ "number": "29",+ "name": "CFETOFF",+ "type": "bidirectional",+ "description": "Charge FET disable input (low disables CHG/PCHG), SPI chip select, thermistor, or digital I/O (VSS-0.3 to VSS+6 V, or VSS-0.2 to VREG18 + 0.3 V for ADC/thermistor)."+ },+ {+ "number": "30",+ "name": "DFETOFF",+ "type": "bidirectional",+ "description": "Discharge FET disable input (low disables DSG/PDSG or both in BOTHOFF mode), thermistor, or digital I/O (VSS-0.3 to VSS+6 V, or VSS-0.2 to VREG18 + 0.3 V for ADC/thermistor)."+ },+ {+ "number": "31",+ "name": "DCHG",+ "type": "bidirectional",+ "description": "Charge FET fault status open-drain output or thermistor/digital I/O (VSS-0.3 to VSS+6 V, or VSS-0.2 to VREG18 + 0.3 V for ADC/thermistor)."+ },+ {+ "number": "32",+ "name": "DDSG",+ "type": "bidirectional",+ "description": "Discharge FET fault status open-drain output or thermistor/digital I/O (VSS-0.3 to VSS+6 V, or VSS-0.2 to VREG18 + 0.3 V for ADC/thermistor)."+ },+ {+ "number": "33",+ "name": "RST_SHUT",+ "type": "input",+ "description": "Reset or shutdown digital input, VSS-0.3 to VSS+6 V logic level, with >1 second assertion triggering SHUTDOWN mode."+ },+ {+ "number": "34",+ "name": "REG2",+ "type": "power_out",+ "description": "Second programmable LDO output (1.8 V / 2.5 V / 3.0 V / 3.3 V / 5.0 V selectable), providing up to 45 mA with 47 to 80 mA short-circuit current limit."+ },+ {+ "number": "35",+ "name": "REG1",+ "type": "power_out",+ "description": "First programmable LDO output (1.8 V / 2.5 V / 3.0 V / 3.3 V / 5.0 V selectable), providing up to 45 mA with 47 to 80 mA short-circuit current limit."+ },+ {+ "number": "36",+ "name": "REGIN",+ "type": "input",+ "description": "LDO supply input providing ~5.5 V from internal pre-regulator or external source for REG1 and REG2, with voltage range maximum of VSS-0.3 or VBREG-5.5 to minimum of VSS+6 or VBAT+0.3."+ },+ {+ "number": "37",+ "name": "BREG",+ "type": "output",+ "description": "Pre-regulator base drive for external NPN BJT, maximum output current 2.5 to 3.33 mA at short circuit."+ },+ {+ "number": "38",+ "name": "FUSE",+ "type": "bidirectional",+ "description": "Fuse drive output (VSS-0.3 to minimum of VSS+20 or VBAT+0.3 V) and secondary protector sense input (VSS-0.3 to VSS+6 V with maximum 2 mA current limit)."+ },+ {+ "number": "39",+ "name": "PDSG",+ "type": "output",+ "description": "Predischarge PFET gate control output, voltage approximately VBAT to VBAT-0.5 V depending on supply level."+ },+ {+ "number": "40",+ "name": "PCHG",+ "type": "output",+ "description": "Precharge PFET gate control output, voltage approximately VPACK to VPACK-0.5 V depending on supply level."+ },+ {+ "number": "41",+ "name": "LD",+ "type": "bidirectional",+ "description": "Load detect pin for pack removal sensing (VSS-0.3 to VSS+85 V) or current source output in SHUTDOWN mode, with internal pullup current 35 to 172 µA."+ },+ {+ "number": "42",+ "name": "PACK",+ "type": "input",+ "description": "PACK+ voltage sense input measuring top-of-stack after protection FETs, VSS-0.3 to VSS+85 V, with ±0.5 V measurement accuracy after calibration."+ },+ {+ "number": "43",+ "name": "DSG",+ "type": "output",+ "description": "Discharge NFET gate drive output, VSS-0.3 to VSS+85 V range, gate-source voltage 4.5 to 7 V (low overdrive) or 10 to 13 V (high overdrive) relative to BAT."+ },+ {+ "number": "44",+ "name": "NC",+ "type": "unconnected",+ "description": "This pin is not connected to silicon."+ },+ {+ "number": "45",+ "name": "CHG",+ "type": "output",+ "description": "Charge NFET gate drive output, VSS-0.3 to VSS+85 V range, gate-source voltage 4.5 to 7 V (low overdrive) or 10 to 13 V (high overdrive) relative to BAT."+ },+ {+ "number": "46",+ "name": "CP1",+ "type": "bidirectional",+ "description": "Charge pump external capacitor connection (100 to 2200 nF recommended), voltage range VBAT-0.3 to minimum of VSS+85 or VBAT+15 V."+ },+ {+ "number": "47",+ "name": "BAT",+ "type": "power_in",+ "description": "Primary power supply input from battery stack top through series diode, VSS-0.3 to VSS+85 V absolute maximum, typical 4.7 to 55 V operating range."+ },+ {+ "number": "48",+ "name": "VC10",+ "type": "input",+ "description": "Tenth cell top-of-stack sense voltage input, measuring between maximum of VSS-0.3 and VC9-0.3 to VSS+85 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 85,+ "cost_usd": 1.0335,+ "at": "2026-09-23T18:37:37"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/bq76942",+ "pages": 85,+ "sha256": "a976a88e92abb957",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 48,+ "described": 48,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}