bd9e104fj-e2

@@ -0,0 +1,47 @@+# BD9E104FJ-E2++**ROHM** · DC-DC Converters · SOIC-8++BD9E104FJ-E2 from ROHM, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | BOOT | passive | Bootstrap capacitor pin. Connect a 0.1 µF ceramic capacitor between BOOT and SW; the capacitor voltage supplies the gate drive for the internal high-side MOSFET. Absolute maximum voltage from GND to BOOT is 35.0 V. |+| 2 | VIN | power_in | Power supply input for the switching regulator and internal control circuits. Operating range 7.0 V to 26.0 V (absolute max −0.3 V to +30.0 V). A 10 µF ceramic decoupling capacitor is recommended close to this pin. |+| 3 | EN | input | Enable input. Drive high (≥ 2.5 V) to enable the converter; drive low (≤ 0.8 V) to force shutdown mode. Must not be left floating. Absolute maximum EN voltage is −0.3 V to +30.0 V. |+| 4 | AGND | power_in | Analog ground for the internal control circuitry. Should be connected to the system ground plane and typically tied to PGND (pin 7) at a single low-impedance point. |+| 5 | FB | input | Feedback input to the internal gm error amplifier. Connect to an external resistor divider from VOUT to set the output voltage (reference 0.8 V typ; output range 1.0 V to VIN × 0.5). Also monitored by SCP (< 0.56 V typ) and OVP (> 1.04 V typ). |+| 6 | COMP | output | Error amplifier output and PWM comparator input. Connect an external RC network (phase-compensation components) from COMP to AGND to shape the control-loop response. |+| 7 | PGND | power_in | Power ground for the output stage of the switching regulator (return for the low-side MOSFET). Route with wide, low-impedance copper directly to the input and output capacitor grounds. |+| 8 | SW | power_out | Switch node. Common connection of the high-side MOSFET source and low-side MOSFET drain. Connect the output inductor here (accounting for DC-superimposition characteristic) and the bootstrap capacitor between SW and BOOT. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | ROHM |+| Package | SOIC-8 |+| Category | PMIC |+| Pins | 8 |++## Ordering variants++- `BD9E104FJ-E2`++## CAD (KiCad official)++- Symbol: `BD9E104FJ-E2`+- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`+- 3D model: SOIC-8 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [ROHM datasheet](docs/bd9e104fj-e2-datasheet.pdf) (None pp, sha256 `b6666dc1fe723e70`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/bd9e104fj-e2-datasheet.pdf)

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