component
BD90640EFJ-CE2
Public Made by Adomby adom
ROHM DC-DC Converters, ESOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+10−7@@ -32,19 +32,19 @@ "number": "1", "name": "RT", "type": "passive",- "description": "Switching frequency setting resistor connection. Connect resistor R_RT (22 k\u03a9-330 k\u03a9) from RT to GND to set f_SW between 50 kHz and 600 kHz (\u224827 k\u03a9 \u2192 500 kHz). Internal reference on RT is \u22480.8 V."+ "description": "Switching frequency setting resistor connection. Connect resistor R_RT (22 kΩ-330 kΩ) from RT to GND to set f_SW between 50 kHz and 600 kHz (≈27 kΩ → 500 kHz). Internal reference on RT is ≈0.8 V." }, { "number": "2", "name": "SW", "type": "power_out",- "description": "Switching output. Drain of the integrated P-ch Power MOSFET (R_ON 0.16 \u03a9 typ). Connect to the external inductor / catch diode node. Rated 4 A max output switch current for BD90640; withstands the full V_IN swing."+ "description": "Switching output. Drain of the integrated P-ch Power MOSFET (R_ON 0.16 Ω typ). Connect to the external inductor / catch diode node. Rated 4 A max output switch current for BD90640; withstands the full V_IN swing." }, { "number": "3", "name": "EN/SYNC", "type": "input",- "description": "Enable / external clock synchronization input. IC is enabled when V_EN/SYNC > 2.6 V (typ threshold 1.9 V) and shut down when < 0.8 V. Also accepts an external clock to synchronize the internal oscillator within \u00b120 % of the RT-programmed frequency. Absolute max V_EN/SYNC \u2264 V_IN."+ "description": "Enable / external clock synchronization input. IC is enabled when V_EN/SYNC > 2.6 V (typ threshold 1.9 V) and shut down when < 0.8 V. Also accepts an external clock to synchronize the internal oscillator within ±20 % of the RT-programmed frequency. Absolute max V_EN/SYNC ≤ V_IN." }, { "number": "4",@@ -56,7 +56,7 @@ "number": "5", "name": "VC", "type": "output",- "description": "Error amplifier output / loop compensation node. Connect external R-C phase-compensation network from VC to GND. Internal source/sink currents \u00b154 \u00b5A typ; g_m \u2248 270 \u00b5A/V. Absolute max 7 V."+ "description": "Error amplifier output / loop compensation node. Connect external R-C phase-compensation network from VC to GND. Internal source/sink currents ±54 µA typ; g_m ≈ 270 µA/V. Absolute max 7 V." }, { "number": "6",@@ -68,13 +68,13 @@ "number": "7", "name": "PVIN", "type": "power_in",- "description": "Power stage supply input feeding the source of the integrated P-ch Power MOSFET. Must be tied to VIN (pin 6) externally. Bypass with a low-ESR ceramic capacitor (\u22652.4 \u00b5F effective) close to the pin."+ "description": "Power stage supply input feeding the source of the integrated P-ch Power MOSFET. Must be tied to VIN (pin 6) externally. Bypass with a low-ESR ceramic capacitor (≥2.4 µF effective) close to the pin." }, { "number": "8", "name": "FB", "type": "input",- "description": "Output voltage feedback input to the error amplifier. Regulated to V_REF = 0.800 V (\u00b12 % over \u221240 \u00b0C to +125 \u00b0C). Set output voltage with a resistor divider from V_O to FB to GND. Input bias current \u00b11 \u00b5A max; absolute max 7 V."+ "description": "Output voltage feedback input to the error amplifier. Regulated to V_REF = 0.800 V (±2 % over −40 °C to +125 °C). Set output voltage with a resistor divider from V_O to FB to GND. Input bias current ±1 µA max; absolute max 7 V." } ], "provenance": {@@ -160,5 +160,8 @@ "docs/bd90640efj-ce2-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ]+ ],+ "visibility": {+ "public": true+ } }