component
ATTINY43U-MU
Public Made by Adomby adom
Microchip Tech Microcontrollers (MCU/MPU/SOC), QFN-20-EP(4x4). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+212−8@@ -1,13 +1,222 @@ {+ "schema_version": 1,+ "type": "component", "slug": "attiny43u-mu",+ "title": "ATTINY43U-MU",+ "brief": "Microchip Tech Microcontrollers (MCU/MPU/SOC), QFN-20-EP(4x4). Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "Microchip Tech Microcontrollers (MCU/MPU/SOC), QFN-20-EP(4x4). Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "embedded processors & controllers", "attiny43u-mu" ],+ "component": {+ "mpn": "ATTINY43U-MU",+ "manufacturer": "Microchip Tech",+ "package": "QFN-20-EP(4x4)",+ "pin_count": 21,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588940482658881536",+ "parts": {+ "symbol": "attiny43u-mu.kicad_sym",+ "footprint": "attiny43u-mu.kicad_mod",+ "model_3d": "attiny43u-mu.glb",+ "model_3d_step": "attiny43u-mu.step",+ "lbr": "attiny43u-mu.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "PB2",+ "type": "bidirectional",+ "description": "Port B bit 2. General-purpose I/O with internal pull-up. Alternate functions: OC0B (Timer/Counter0 compare match B output / PWM) and PCINT10 (pin-change interrupt). Tri-stated during reset. Vih \u2265 0.6\u00b7VCC, Vil \u2264 0.3\u00b7VCC; ~40 mA sink/source per pin (symmetrical drive)."+ },+ {+ "number": "2",+ "name": "PB3",+ "type": "bidirectional",+ "description": "Port B bit 3. General-purpose I/O with internal pull-up. Alternate functions: T1 (Timer/Counter1 external clock input), CLKO (system clock output when CKOUT fuse is programmed) and PCINT11."+ },+ {+ "number": "3",+ "name": "PB4",+ "type": "bidirectional",+ "description": "Port B bit 4. General-purpose I/O with internal pull-up. Alternate functions: DI (USI three-wire data-input / SPI MOSI), OC1A (Timer/Counter1 PWM output A) and PCINT12."+ },+ {+ "number": "4",+ "name": "PB5",+ "type": "bidirectional",+ "description": "Port B bit 5. General-purpose I/O with internal pull-up. Alternate functions: DO (USI three-wire data-output / SPI MISO), OC1B (Timer/Counter1 PWM output B) and PCINT13."+ },+ {+ "number": "5",+ "name": "PB6",+ "type": "bidirectional",+ "description": "Port B bit 6. General-purpose I/O with internal pull-up. Alternate functions: USCK (USI clock line for three-wire/SPI mode), SCL (USI clock line for two-wire/I\u00b2C mode) and PCINT14."+ },+ {+ "number": "6",+ "name": "PB7",+ "type": "bidirectional",+ "description": "Port B bit 7. General-purpose I/O with internal pull-up. Alternate functions: INT0 (external interrupt request 0 input) and PCINT15."+ },+ {+ "number": "7",+ "name": "VCC",+ "type": "power_in",+ "description": "Digital supply voltage. 1.8 - 5.5 V when the on-chip boost converter is bypassed. When the boost converter is used, VCC is driven internally from VBAT (0.7 - 1.8 V) via the LSW inductor node; VCC is then the boosted rail. Decouple close to the pin."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for the whole device. Tie the QFN exposed pad to the same GND net."+ },+ {+ "number": "9",+ "name": "LSW",+ "type": "passive",+ "description": "Boost-converter switching node - connects to the external boost inductor (the other end goes to VBAT). Internally the low-side switch of the boost converter pulls this node to GND at the switching frequency. Tie directly to GND if the boost converter will be permanently disabled."+ },+ {+ "number": "10",+ "name": "VBAT",+ "type": "power_in",+ "description": "Battery / low-voltage input to the on-chip boost converter (0.7 - 1.8 V nominal). Also the far end of the boost inductor. Tie to GND if the boost converter will be permanently disabled."+ },+ {+ "number": "11",+ "name": "PA0",+ "type": "bidirectional",+ "description": "Port A bit 0. General-purpose I/O with internal pull-up. Alternate functions: ADC0 (10-bit ADC single-ended channel 0) and PCINT0."+ },+ {+ "number": "12",+ "name": "PA1",+ "type": "bidirectional",+ "description": "Port A bit 1. General-purpose I/O with internal pull-up. Alternate functions: ADC1 (10-bit ADC channel 1) and PCINT1."+ },+ {+ "number": "13",+ "name": "PA2",+ "type": "bidirectional",+ "description": "Port A bit 2. General-purpose I/O with internal pull-up. Alternate functions: ADC2 (10-bit ADC channel 2) and PCINT2."+ },+ {+ "number": "14",+ "name": "PA3",+ "type": "bidirectional",+ "description": "Port A bit 3. General-purpose I/O with internal pull-up. Alternate functions: ADC3 (10-bit ADC channel 3) and PCINT3."+ },+ {+ "number": "15",+ "name": "PA4",+ "type": "bidirectional",+ "description": "Port A bit 4. General-purpose I/O with internal pull-up. Alternate functions: AIN0 (positive input of the on-chip analog comparator) and PCINT4."+ },+ {+ "number": "16",+ "name": "PA5",+ "type": "bidirectional",+ "description": "Port A bit 5. General-purpose I/O with internal pull-up. Alternate functions: AIN1 (negative input of the on-chip analog comparator) and PCINT5."+ },+ {+ "number": "17",+ "name": "PA6",+ "type": "bidirectional",+ "description": "Port A bit 6. General-purpose I/O with internal pull-up. Alternate functions: CLKI (external clock input when the External Clock system-clock source is selected by fuses) and PCINT6."+ },+ {+ "number": "18",+ "name": "PA7",+ "type": "bidirectional",+ "description": "Port A bit 7 / RESET. When the RSTDISBL fuse is unprogrammed this pin is the active-low external RESET input (a low pulse longer than the minimum pulse length triggers a reset even without a running clock). Programming RSTDISBL (=0) turns the pin into a normal GPIO - but then further ISP is only possible via High-Voltage Serial Programming. Also carries the debugWIRE (dW) signal for on-chip debug/programming and PCINT7."+ },+ {+ "number": "19",+ "name": "PB0",+ "type": "bidirectional",+ "description": "Port B bit 0. General-purpose I/O with internal pull-up. Alternate functions: T0 (Timer/Counter0 external clock input) and PCINT8."+ },+ {+ "number": "20",+ "name": "PB1",+ "type": "bidirectional",+ "description": "Port B bit 1. General-purpose I/O with internal pull-up. Alternate functions: OC0A (Timer/Counter0 compare match A output / PWM) and PCINT9."+ },+ {+ "number": "EP",+ "name": "EP",+ "type": "power_in",+ "description": "Exposed thermal / centre pad on the underside of the QFN/MLF package. Per the datasheet note, must be soldered to ground (tie to GND net)."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588940482658881536",+ "pages": 210,+ "sha256": "5e4f91d02c1ae2a1",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 21,+ "described": 21,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Microchip Tech",+ "Package": "QFN-20-EP(4x4)",+ "Category": "Embedded Processors & Controllers",+ "Pins": "21"+ }+ },+ "variants": [+ {+ "mpn": "ATTINY43U-MU",+ "kind": "packaging"+ },+ {+ "mpn": "ATTINY43U-MUR",+ "kind": "packaging"+ },+ {+ "mpn": "ATTINY43U-MUSU",+ "kind": "packaging"+ },+ {+ "mpn": "ATTINY43U-MUSUR",+ "kind": "packaging"+ }+ ],+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "attiny43u-mu"+ ],+ "discovery_pitch": "ATTINY43U-MU (Microchip Tech) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +234,5 @@ "docs/attiny43u-mu-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }