ATM90E32AS-AU-R

@@ -53,7 +53,7 @@         "number": "1",         "name": "AVDD",         "type": "power_in",-        "description": "Analog power supply (3.3V); should be connected to DVDD and decoupled with a 0.1\u03bcF capacitor."+        "description": "Analog power supply (3.3V); should be connected to DVDD and decoupled with a 0.1μF capacitor."       },       {         "number": "2",@@ -65,37 +65,37 @@         "number": "3",         "name": "I1P",         "type": "input",-        "description": "Positive input to differential ADC channel 1 for current sampling; accepts signals from 120\u03bcV to 720mV at 1x PGA gain."+        "description": "Positive input to differential ADC channel 1 for current sampling; accepts signals from 120μV to 720mV at 1x PGA gain."       },       {         "number": "4",         "name": "I1N",         "type": "input",-        "description": "Negative input to differential ADC channel 1 for current sampling; accepts signals from 120\u03bcV to 720mV at 1x PGA gain."+        "description": "Negative input to differential ADC channel 1 for current sampling; accepts signals from 120μV to 720mV at 1x PGA gain."       },       {         "number": "5",         "name": "I2P",         "type": "input",-        "description": "Positive input to differential ADC channel 2 for current sampling; accepts signals from 120\u03bcV to 720mV at 1x PGA gain."+        "description": "Positive input to differential ADC channel 2 for current sampling; accepts signals from 120μV to 720mV at 1x PGA gain."       },       {         "number": "6",         "name": "I2N",         "type": "input",-        "description": "Negative input to differential ADC channel 2 for current sampling; accepts signals from 120\u03bcV to 720mV at 1x PGA gain."+        "description": "Negative input to differential ADC channel 2 for current sampling; accepts signals from 120μV to 720mV at 1x PGA gain."       },       {         "number": "7",         "name": "I3P",         "type": "input",-        "description": "Positive input to differential ADC channel 3 for current sampling; accepts signals from 120\u03bcV to 720mV at 1x PGA gain."+        "description": "Positive input to differential ADC channel 3 for current sampling; accepts signals from 120μV to 720mV at 1x PGA gain."       },       {         "number": "8",         "name": "I3N",         "type": "input",-        "description": "Negative input to differential ADC channel 3 for current sampling; accepts signals from 120\u03bcV to 720mV at 1x PGA gain."+        "description": "Negative input to differential ADC channel 3 for current sampling; accepts signals from 120μV to 720mV at 1x PGA gain."       },       {         "number": "9",@@ -113,7 +113,7 @@         "number": "11",         "name": "Vref",         "type": "power_in",-        "description": "Reference voltage output (1.2V nominal) for on-chip reference circuit; should be decoupled with 4.7\u03bcF and 0.1\u03bcF capacitors."+        "description": "Reference voltage output (1.2V nominal) for on-chip reference circuit; should be decoupled with 4.7μF and 0.1μF capacitors."       },       {         "number": "12",@@ -125,37 +125,37 @@         "number": "13",         "name": "V1P",         "type": "input",-        "description": "Positive input to differential ADC channel for voltage sampling of phase 1; accepts signals from 120\u03bcV to 720mV at 1x PGA gain."+        "description": "Positive input to differential ADC channel for voltage sampling of phase 1; accepts signals from 120μV to 720mV at 1x PGA gain."       },       {         "number": "14",         "name": "V1N",         "type": "input",-        "description": "Negative input to differential ADC channel for voltage sampling of phase 1; accepts signals from 120\u03bcV to 720mV at 1x PGA gain."+        "description": "Negative input to differential ADC channel for voltage sampling of phase 1; accepts signals from 120μV to 720mV at 1x PGA gain."       },       {         "number": "15",         "name": "V2P",         "type": "input",-        "description": "Positive input to differential ADC channel for voltage sampling of phase 2; accepts signals from 120\u03bcV to 720mV at 1x PGA gain."+        "description": "Positive input to differential ADC channel for voltage sampling of phase 2; accepts signals from 120μV to 720mV at 1x PGA gain."       },       {         "number": "16",         "name": "V2N",         "type": "input",-        "description": "Negative input to differential ADC channel for voltage sampling of phase 2; accepts signals from 120\u03bcV to 720mV at 1x PGA gain."+        "description": "Negative input to differential ADC channel for voltage sampling of phase 2; accepts signals from 120μV to 720mV at 1x PGA gain."       },       {         "number": "17",         "name": "V3P",         "type": "input",-        "description": "Positive input to differential ADC channel for voltage sampling of phase 3; accepts signals from 120\u03bcV to 720mV at 1x PGA gain."+        "description": "Positive input to differential ADC channel for voltage sampling of phase 3; accepts signals from 120μV to 720mV at 1x PGA gain."       },       {         "number": "18",         "name": "V3N",         "type": "input",-        "description": "Negative input to differential ADC channel for voltage sampling of phase 3; accepts signals from 120\u03bcV to 720mV at 1x PGA gain."+        "description": "Negative input to differential ADC channel for voltage sampling of phase 3; accepts signals from 120μV to 720mV at 1x PGA gain."       },       {         "number": "19",@@ -167,7 +167,7 @@         "number": "20",         "name": "OSCI",         "type": "input",-        "description": "Crystal oscillator input or external clock source; accepts 16.384 MHz clock with \u00b120 ppm accuracy and 10pF-20pF load capacitance."+        "description": "Crystal oscillator input or external clock source; accepts 16.384 MHz clock with ±20 ppm accuracy and 10pF-20pF load capacitance."       },       {         "number": "21",@@ -197,25 +197,25 @@         "number": "25",         "name": "CF1",         "type": "output",-        "description": "All-phase-sum total active energy pulse output; generates pulse with 80ms width when period \u2265160ms, or T/2 width for 10ms-160ms period."+        "description": "All-phase-sum total active energy pulse output; generates pulse with 80ms width when period ≥160ms, or T/2 width for 10ms-160ms period."       },       {         "number": "26",         "name": "CF2",         "type": "output",-        "description": "All-phase-sum total reactive or apparent energy pulse output (configurable via CF2varh bit); generates pulse with 80ms width when period \u2265160ms, or T/2 width for 10ms-160ms period."+        "description": "All-phase-sum total reactive or apparent energy pulse output (configurable via CF2varh bit); generates pulse with 80ms width when period ≥160ms, or T/2 width for 10ms-160ms period."       },       {         "number": "27",         "name": "CF3",         "type": "output",-        "description": "All-phase-sum total active fundamental energy pulse output; generates pulse with 80ms width when period \u2265160ms, or T/2 width for 10ms-160ms period."+        "description": "All-phase-sum total active fundamental energy pulse output; generates pulse with 80ms width when period ≥160ms, or T/2 width for 10ms-160ms period."       },       {         "number": "28",         "name": "CF4",         "type": "output",-        "description": "All-phase-sum total active harmonic energy pulse output; generates pulse with 80ms width when period \u2265160ms, or T/2 width for 10ms-160ms period."+        "description": "All-phase-sum total active harmonic energy pulse output; generates pulse with 80ms width when period ≥160ms, or T/2 width for 10ms-160ms period."       },       {         "number": "29",@@ -293,19 +293,19 @@         "number": "41",         "name": "RESET",         "type": "input",-        "description": "Active-low reset input (LVTTL); resets chip registers and state when asserted, should connect through 0.1\u03bcF capacitor and 10k\u03a9 resistor to VDD."+        "description": "Active-low reset input (LVTTL); resets chip registers and state when asserted, should connect through 0.1μF capacitor and 10kΩ resistor to VDD."       },       {         "number": "42",         "name": "VDD18",         "type": "power_out",-        "description": "1.8V regulated digital power supply output from on-chip regulator; must be connected together with pin 43 and bypassed with 10\u03bcF capacitor."+        "description": "1.8V regulated digital power supply output from on-chip regulator; must be connected together with pin 43 and bypassed with 10μF capacitor."       },       {         "number": "43",         "name": "VDD18",         "type": "power_out",-        "description": "1.8V regulated digital power supply output from on-chip regulator; must be connected together with pin 42 and bypassed with 10\u03bcF capacitor."+        "description": "1.8V regulated digital power supply output from on-chip regulator; must be connected together with pin 42 and bypassed with 10μF capacitor."       },       {         "number": "44",@@ -335,7 +335,7 @@         "number": "48",         "name": "DVDD",         "type": "power_in",-        "description": "Digital power supply (3.3V); should be decoupled with 10\u03bcF and 0.1\u03bcF capacitors."+        "description": "Digital power supply (3.3V); should be decoupled with 10μF and 0.1μF capacitors."       }     ],     "provenance": {@@ -370,6 +370,46 @@     "viewers": {       "symbol": "viewers/symbol.html",       "footprint": "viewers/footprint.html"-    }+    },+    "models_3d": [+      {+        "file": "atm90e32as-au-r.step",+        "role": "plain",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          9.0,+          9.0,+          1.1+        ],+        "zmin_mm": -0.0,+        "centre_offset_mm": 0.0,+        "footprint_binding": "identity",+        "sha256": "14ca7676e4932e92f0eca0c6d56ce3018cd28a2531204a70ab7bbacb3eeb3cf5",+        "checked": "2026-10-07",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      },+      {+        "file": "atm90e32as-au-r-etched.step",+        "role": "eda",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          9.0,+          9.0,+          1.1+        ],+        "zmin_mm": -0.0,+        "centre_offset_mm": 0.0,+        "footprint_binding": "identity",+        "sha256": "e65a2f736aa01631c24bd94b60b90f3329e815e772631a75ad665f97758426a9",+        "checked": "2026-10-07",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      }+    ]   }-}\ No newline at end of file+}