AT32F415CBT7

@@ -0,0 +1,101 @@+# AT32F415CBT7++**ARTERY** · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)++AT32F415CBT7 from ARTERY, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VBAT | power_in | Backup domain supply. Powers LEXT oscillator, ERTC and 20x 32-bit battery-backed BPR registers when VDD is absent. |+| 2 | PC13/TAMPER-RTC | bidirectional | GPIO PC13 with alternate TAMPER-RTC. Powered from backup switch; limited to ~3 mA source current so cannot drive LEDs directly. |+| 3 | PC14/LEXT_IN | bidirectional | GPIO PC14, default alternate is LEXT_IN (32 kHz low-speed external crystal input). |+| 4 | PC15/LEXT_OUT | bidirectional | GPIO PC15, default alternate is LEXT_OUT (32 kHz LSE crystal output). |+| 5 | PD0/HEXT_IN | bidirectional | Default HEXT_IN (4-25 MHz high-speed external crystal input). Can be remapped to GPIO PD0 by firmware. |+| 6 | PD1/HEXT_OUT | bidirectional | Default HEXT_OUT (HEXT crystal driver output). Can be remapped to GPIO PD1 by firmware. |+| 7 | NRST | bidirectional | Active-low bidirectional reset. External pull-up to VDD; driven low on POR/LVR/watchdog/software reset. |+| 8 | VSSA/VREF- | power_in | Analog ground / ADC negative reference. Tie to VSS with a low-impedance path. |+| 9 | VDDA/VREF+ | power_in | Analog supply / ADC positive reference (2.6-3.6 V). Decouple to VSSA. |+| 10 | PA0-WKUP | bidirectional | GPIO PA0 with WKUP wake-from-standby, ADC1_IN0, CMP1 IN/OUT, USART2_CTS, TMR2/5 channels and TMR1_EXT remap. |+| 11 | PA1 | bidirectional | GPIO PA1. Alt: ADC1_IN1, CMP1_INP1, USART2_RTS, TMR2_CH2, TMR5_CH2. |+| 12 | PA2 | bidirectional | GPIO PA2. Alt: ADC1_IN2, CMP2 IN/OUT, USART2_TX, TMR2_CH3, TMR5_CH3, TMR9_CH1; SDIO1_CK remap. |+| 13 | PA3 | bidirectional | GPIO PA3. Alt: ADC1_IN3, CMP2_INP1, USART2_RX, TMR2_CH4, TMR5_CH4, TMR9_CH2; SDIO1_CMD remap. |+| 14 | PA4 | bidirectional | GPIO PA4 (5 V-tolerant? no; standard IO). Alt: ADC1_IN4, CMP1/2_INM4, USART2_CK, SPI1_CS, I2S1_WS; SDIO1_D4/D0 remap. |+| 15 | PA5 | bidirectional | GPIO PA5. Alt: ADC1_IN5, CMP1_INP0, CMP1/2_INM5, SPI1_SCK, I2S1_CK; USART3_CK / SDIO1_D5/D1 remap. |+| 16 | PA6 | bidirectional | GPIO PA6. Alt: ADC1_IN6, SPI1_MISO, TMR3_CH1; CMP1_OUT / USART3_RX / SDIO1_D6/D2 / TMR1_BRK / TMR10_CH1 remap. |+| 17 | PA7 | bidirectional | GPIO PA7. Alt: ADC1_IN7, CMP2_INP0, SPI1_MOSI, I2S1_SD, TMR3_CH2; CMP2_OUT / USART3_TX / SDIO1_D7/D3 / TMR1_CH1C / TMR11_CH1 remap. |+| 18 | PB0 | bidirectional | GPIO PB0. Alt: ADC1_IN8, I2S1_MCK, TMR3_CH3; USART3_RTS / TMR1_CH2C remap. |+| 19 | PB1 | bidirectional | GPIO PB1. Alt: ADC1_IN9, TMR3_CH4; USART3_CTS / TMR1_CH3C remap. |+| 20 | PB2/BOOT1 | bidirectional | GPIO PB2 (5 V-tolerant), also sampled as BOOT1 at reset for boot-mode selection. |+| 21 | PB10 | bidirectional | GPIO PB10 (5 V-tolerant). Alt: I2C2_SCL, USART3_TX; TMR2_CH3 remap. |+| 22 | PB11 | bidirectional | GPIO PB11 (5 V-tolerant). Alt: I2C2_SDA, USART3_RX; TMR2_CH4 remap. |+| 23 | VSS | power_in | Digital ground. |+| 24 | VDD | power_in | Digital supply, 2.6-3.6 V. |+| 25 | PB12 | bidirectional | GPIO PB12 (5 V-tolerant). Alt: USART3_CK, I2C2_SMBA, SPI2_CS, I2S2_WS, TMR1_BRK. |+| 26 | PB13 | bidirectional | GPIO PB13 (5 V-tolerant). Alt: TMR1_CH1C, USART3_CTS, SPI2_SCK, I2S2_CK. |+| 27 | PB14 | bidirectional | GPIO PB14 (5 V-tolerant). Alt: TMR1_CH2C, USART3_RTS, SPI2_MISO; TMR9_CH1 remap. |+| 28 | PB15 | bidirectional | GPIO PB15 (5 V-tolerant). Alt: TMR1_CH3C, ERTC_REFIN, SPI2_MOSI, I2S2_SD; TMR9_CH2 remap. |+| 29 | PA8 | bidirectional | GPIO PA8 (5 V-tolerant). Alt: OTGFS1_SOF, CLKOUT, USART1_CK, TMR1_CH1; I2C2_SCL remap. |+| 30 | PA9 | bidirectional | GPIO PA9 (5 V-tolerant). Alt: OTGFS1_VBUS, USART1_TX, TMR1_CH2; I2C2_SMBA remap. |+| 31 | PA10 | bidirectional | GPIO PA10. Alt: OTGFS1_ID, USART1_RX, TMR1_CH3. |+| 32 | PA11 | bidirectional | GPIO PA11. Alt: OTGFS1_D-, USART1_CTS, CAN1_RX, TMR1_CH4; CMP1_OUT remap. |+| 33 | PA12 | bidirectional | GPIO PA12. Alt: OTGFS1_D+, USART1_RTS, CAN1_TX, TMR1_EXT; CMP2_OUT remap. |+| 34 | PA13/JTMS-SWDIO | bidirectional | Default JTMS/SWDIO debug pin (5 V-tolerant). Can be freed to GPIO PA13 by remap. |+| 35 | PF6 | bidirectional | GPIO PF6 (5 V-tolerant). Remap: I2C1_SCL / I2C2_SCL. |+| 36 | PF7 | bidirectional | GPIO PF7 (5 V-tolerant). Remap: I2C1_SDA / I2C2_SDA. |+| 37 | PA14/JTCK-SWCLK | bidirectional | Default JTCK/SWCLK debug clock (5 V-tolerant). Can be freed to GPIO PA14 by remap. |+| 38 | PA15/JTDI | bidirectional | Default JTDI debug pin (5 V-tolerant). Remap: PA15 GPIO, SPI1/2_CS, I2S1/2_WS, TMR2_CH1, TMR2_EXT. |+| 39 | PB3/JTDO | bidirectional | Default JTDO/SWO debug pin (5 V-tolerant). Remap: PB3 GPIO, SPI1/2_SCK, I2S1/2_CK, TMR2_CH2. |+| 40 | PB4/NJTRST | bidirectional | Default NJTRST JTAG reset (5 V-tolerant, active low). Remap: PB4 GPIO, SPI1/2_MISO, I2C2_SDA, TMR3_CH1. |+| 41 | PB5 | bidirectional | GPIO PB5 (5 V-tolerant). Alt: I2C1_SMBA; remap SPI1_MOSI/I2S1_SD, SPI2_MOSI/I2S2_SD, TMR3_CH2. |+| 42 | PB6 | bidirectional | GPIO PB6 (5 V-tolerant). Alt: I2C1_SCL, TMR4_CH1; USART1_TX / I2S1_MCK remap. |+| 43 | PB7 | bidirectional | GPIO PB7 (5 V-tolerant). Alt: I2C1_SDA, TMR4_CH2; USART1_RX remap. |+| 44 | BOOT0 | input | Boot-mode select input sampled at reset (with BOOT1/PB2) to select flash, system-memory (bootloader), or SRAM boot. |+| 45 | PB8 | bidirectional | GPIO PB8 (5 V-tolerant). Alt: SDIO1_D4, TMR4_CH3, TMR10_CH1; I2C1_SCL / CAN1_RX remap. |+| 46 | PB9 | bidirectional | GPIO PB9 (5 V-tolerant). Alt: SDIO1_D5, TMR4_CH4, TMR11_CH1; I2C1_SDA / CAN1_TX remap. |+| 47 | VSS | power_in | Digital ground. |+| 48 | VDD | power_in | Digital supply, 2.6-3.6 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | ARTERY |+| Package | LQFP-48(7x7) |+| Category | MCU |+| Pins | 48 |++## Ordering variants++- `AT32F415CBT7CBT7`+- `AT32F415CBT7CCT7`+- `AT32F415CBT7C8T7`+- `AT32F415CBT7CBU7`+- `AT32F415CBT7CCU7`+- `AT32F415CBT7RBT7`+- `AT32F415CBT7RBT7-7`+- `AT32F415CBT7RCT7`+- `AT32F415CBT7RCT7-7`+- `AT32F415CBT7R8T7`+- `AT32F415CBT7R8T7-7`+- `AT32F415CBT7KBU7-4`+- `AT32F415CBT7KCU7-4`+- `AT32F415CBT7K8U7-4`++## CAD (KiCad official)++- Symbol: `AT32F415CBT7`+- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`+- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [ARTERY datasheet](docs/at32f415cbt7-datasheet.pdf) (75 pp, sha256 `7bd001051ee57bd1`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/at32f415cbt7-datasheet.pdf)