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Set visibility: public

Ray ·4f797a8ac1 · ·parent 852add6
1 file changed +9−6
page.json+9−6
@@ -32,7 +32,7 @@         "number": "1",         "name": "J3",         "type": "passive",-        "description": "RF port J3. One of the two 'throw' RF ports of the SPDT switch; 50 \u03a9 characteristic impedance. Requires a 100 pF DC-blocking capacitor for >500 MHz operation (larger values for lower frequencies)."+        "description": "RF port J3. One of the two 'throw' RF ports of the SPDT switch; 50 Ω characteristic impedance. Requires a 100 pF DC-blocking capacitor for >500 MHz operation (larger values for lower frequencies)."       },       {         "number": "2",@@ -44,25 +44,25 @@         "number": "3",         "name": "J2",         "type": "passive",-        "description": "RF port J2. The other 'throw' RF port of the SPDT switch; 50 \u03a9 characteristic impedance. Requires a 100 pF DC-blocking capacitor for >500 MHz operation (larger values for lower frequencies)."+        "description": "RF port J2. The other 'throw' RF port of the SPDT switch; 50 Ω characteristic impedance. Requires a 100 pF DC-blocking capacitor for >500 MHz operation (larger values for lower frequencies)."       },       {         "number": "4",         "name": "V1",         "type": "input",-        "description": "DC control voltage input V1. Complementary control with V2 selects the active RF path. VCTL low = 0 to 0.2 V (@ 20 \u03bcA max); VCTL high = 2.0 V (@ 100 \u03bcA max) or 5.0 V (@ 200 \u03bcA max). Absolute maximum range -1.2 V to +8.0 V."+        "description": "DC control voltage input V1. Complementary control with V2 selects the active RF path. VCTL low = 0 to 0.2 V (@ 20 μA max); VCTL high = 2.0 V (@ 100 μA max) or 5.0 V (@ 200 μA max). Absolute maximum range -1.2 V to +8.0 V."       },       {         "number": "5",         "name": "J1",         "type": "passive",-        "description": "RF common port J1 (the 'pole' of the SPDT). Routed to either J2 or J3 depending on the V1/V2 control state; 50 \u03a9 characteristic impedance. Requires a 100 pF DC-blocking capacitor for >500 MHz operation."+        "description": "RF common port J1 (the 'pole' of the SPDT). Routed to either J2 or J3 depending on the V1/V2 control state; 50 Ω characteristic impedance. Requires a 100 pF DC-blocking capacitor for >500 MHz operation."       },       {         "number": "6",         "name": "V2",         "type": "input",-        "description": "DC control voltage input V2. Complementary control with V1 selects the active RF path. VCTL low = 0 to 0.2 V (@ 20 \u03bcA max); VCTL high = 2.0 V (@ 100 \u03bcA max) or 5.0 V (@ 200 \u03bcA max). Absolute maximum range -1.2 V to +8.0 V."+        "description": "DC control voltage input V2. Complementary control with V1 selects the active RF path. VCTL low = 0 to 0.2 V (@ 20 μA max); VCTL high = 2.0 V (@ 100 μA max) or 5.0 V (@ 200 μA max). Absolute maximum range -1.2 V to +8.0 V."       }     ],     "provenance": {@@ -126,5 +126,8 @@     "docs/as179-92lf-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ]+  ],+  "visibility": {+    "public": true+  } }\ No newline at end of file