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orderable attributes: rebuild .lbr with adom-lbr 2.18.0 so MPN, MANUFACTURER and the distributor part numbers reach <technology> (LCSC_PN C133314). The published library carried no attributes at all, so a BOM had nothing to buy from. Distributor PNs matched on exact MPN AND corroborating manufacturer.

Ray ·dd8e3f5056 · ·parent 08734e0
2 files changed +28−8
as169-73lf.lbr+20−2
@@ -60,6 +60,18 @@   <smd name="4" x="1.1375" y="-0.9500" dx="1.3250" dy="0.6000" layer="1"/>   <smd name="5" x="1.1375" y="-0.0000" dx="1.3250" dy="0.6000" layer="1"/>   <smd name="6" x="1.1375" y="0.9500" dx="1.3250" dy="0.6000" layer="1"/>+  <polygon width="0.1200" layer="21">+    <vertex x="-1.4500" y="1.5100"/>+    <vertex x="-1.6900" y="1.8400"/>+    <vertex x="-1.2100" y="1.8400"/>+  </polygon>+  <polygon width="0.1000" layer="51">+    <vertex x="-0.4000" y="1.4500"/>+    <vertex x="0.8000" y="1.4500"/>+    <vertex x="0.8000" y="-1.4500"/>+    <vertex x="-0.8000" y="-1.4500"/>+    <vertex x="-0.8000" y="1.0500"/>+  </polygon>   <wire x1="-0.9100" y1="1.5600" x2="0.9100" y2="1.5600" width="0.1200" layer="21"/>   <wire x1="-0.9100" y1="1.5100" x2="-0.9100" y2="1.5600" width="0.1200" layer="21"/>   <wire x1="-0.9100" y1="-1.5600" x2="-0.9100" y2="-1.5100" width="0.1200" layer="21"/>@@ -68,7 +80,7 @@   <wire x1="0.9100" y1="-1.5600" x2="-0.9100" y2="-1.5600" width="0.1200" layer="21"/>   <text x="0" y="2.212" size="1.27" layer="25" align="bottom-center">&gt;NAME</text>   <text x="0" y="-2.212" size="1.27" layer="27" align="top-center">&gt;VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-1.4500" y="1.5100"/><vertex x="-1.6900" y="1.8400"/><vertex x="-1.2100" y="1.8400"/></polygon></package>+</package> </packages> <symbols> <symbol name="AS169-73LF">@@ -102,7 +114,13 @@         <connect gate="G$1" pin="J1" pad="5"/>         <connect gate="G$1" pin="V1" pad="4"/>       </connects>-      <technologies><technology name=""/></technologies>+      <technologies>+        <technology name="">+          <attribute name="MPN" value="AS169-73LF" constant="no"/>+          <attribute name="MANUFACTURER" value="Skyworks Solutions" constant="no"/>+          <attribute name="LCSC_PN" value="C133314" constant="no"/>+        </technology>+      </technologies>     </device>   </devices> </deviceset>
page.json+8−6
@@ -26,13 +26,15 @@       "model_3d_step": "as169-73lf.step",       "lbr": "as169-73lf.lbr"     },-    "distributor_links": {},+    "distributor_links": {+      "lcsc": "C133314"+    },     "pins": [       {         "number": "1",         "name": "J3",         "type": "passive",-        "description": "RF port J3 (throw 2). 50 Ω RF port; requires an external DC-blocking capacitor (CBL = 100 pF for operation >500 MHz) for positive-voltage operation. Connected to the common port J1 when V2 = HIGH and V1 = LOW."+        "description": "RF port J3 (throw 2). 50 \u03a9 RF port; requires an external DC-blocking capacitor (CBL = 100 pF for operation >500 MHz) for positive-voltage operation. Connected to the common port J1 when V2 = HIGH and V1 = LOW."       },       {         "number": "2",@@ -44,25 +46,25 @@         "number": "3",         "name": "J2",         "type": "passive",-        "description": "RF port J2 (throw 1). 50 Ω RF port; requires an external DC-blocking capacitor (CBL = 100 pF for operation >500 MHz) for positive-voltage operation. Connected to the common port J1 when V1 = HIGH and V2 = LOW."+        "description": "RF port J2 (throw 1). 50 \u03a9 RF port; requires an external DC-blocking capacitor (CBL = 100 pF for operation >500 MHz) for positive-voltage operation. Connected to the common port J1 when V1 = HIGH and V2 = LOW."       },       {         "number": "4",         "name": "V1",         "type": "input",-        "description": "Digital control voltage 1 (complement of V2). VLOW = 0 to 0.2 V @ 20 µA max, VHIGH = 3 V @ 100 µA max to 5 V @ 200 µA max. When V1 = HIGH and V2 = LOW, J1↔J2 is in insertion-loss (through) state."+        "description": "Digital control voltage 1 (complement of V2). VLOW = 0 to 0.2 V @ 20 \u00b5A max, VHIGH = 3 V @ 100 \u00b5A max to 5 V @ 200 \u00b5A max. When V1 = HIGH and V2 = LOW, J1\u2194J2 is in insertion-loss (through) state."       },       {         "number": "5",         "name": "J1",         "type": "passive",-        "description": "Common RF port J1 (pole). 50 Ω RF port; requires an external DC-blocking capacitor (CBL = 100 pF for operation >500 MHz) for positive-voltage operation. Routed to either J2 or J3 based on the V1/V2 control state."+        "description": "Common RF port J1 (pole). 50 \u03a9 RF port; requires an external DC-blocking capacitor (CBL = 100 pF for operation >500 MHz) for positive-voltage operation. Routed to either J2 or J3 based on the V1/V2 control state."       },       {         "number": "6",         "name": "V2",         "type": "input",-        "description": "Digital control voltage 2 (complement of V1). VLOW = 0 to 0.2 V @ 20 µA max, VHIGH = 3 V @ 100 µA max to 5 V @ 200 µA max. When V2 = HIGH and V1 = LOW, J1↔J3 is in insertion-loss (through) state."+        "description": "Digital control voltage 2 (complement of V1). VLOW = 0 to 0.2 V @ 20 \u00b5A max, VHIGH = 3 V @ 100 \u00b5A max to 5 V @ 200 \u00b5A max. When V2 = HIGH and V1 = LOW, J1\u2194J3 is in insertion-loss (through) state."       }     ],     "provenance": {