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Set visibility: public

Ray ·b84bcfe0b8 · ·parent eb35e27
1 file changed +9−6
page.json+9−6
@@ -32,7 +32,7 @@         "number": "1",         "name": "J3",         "type": "passive",-        "description": "RF port J3 (throw 2). 50 \u03a9 RF port; requires an external DC-blocking capacitor (CBL = 100 pF for operation >500 MHz) for positive-voltage operation. Connected to the common port J1 when V2 = HIGH and V1 = LOW."+        "description": "RF port J3 (throw 2). 50 Ω RF port; requires an external DC-blocking capacitor (CBL = 100 pF for operation >500 MHz) for positive-voltage operation. Connected to the common port J1 when V2 = HIGH and V1 = LOW."       },       {         "number": "2",@@ -44,25 +44,25 @@         "number": "3",         "name": "J2",         "type": "passive",-        "description": "RF port J2 (throw 1). 50 \u03a9 RF port; requires an external DC-blocking capacitor (CBL = 100 pF for operation >500 MHz) for positive-voltage operation. Connected to the common port J1 when V1 = HIGH and V2 = LOW."+        "description": "RF port J2 (throw 1). 50 Ω RF port; requires an external DC-blocking capacitor (CBL = 100 pF for operation >500 MHz) for positive-voltage operation. Connected to the common port J1 when V1 = HIGH and V2 = LOW."       },       {         "number": "4",         "name": "V1",         "type": "input",-        "description": "Digital control voltage 1 (complement of V2). VLOW = 0 to 0.2 V @ 20 \u00b5A max, VHIGH = 3 V @ 100 \u00b5A max to 5 V @ 200 \u00b5A max. When V1 = HIGH and V2 = LOW, J1\u2194J2 is in insertion-loss (through) state."+        "description": "Digital control voltage 1 (complement of V2). VLOW = 0 to 0.2 V @ 20 µA max, VHIGH = 3 V @ 100 µA max to 5 V @ 200 µA max. When V1 = HIGH and V2 = LOW, J1↔J2 is in insertion-loss (through) state."       },       {         "number": "5",         "name": "J1",         "type": "passive",-        "description": "Common RF port J1 (pole). 50 \u03a9 RF port; requires an external DC-blocking capacitor (CBL = 100 pF for operation >500 MHz) for positive-voltage operation. Routed to either J2 or J3 based on the V1/V2 control state."+        "description": "Common RF port J1 (pole). 50 Ω RF port; requires an external DC-blocking capacitor (CBL = 100 pF for operation >500 MHz) for positive-voltage operation. Routed to either J2 or J3 based on the V1/V2 control state."       },       {         "number": "6",         "name": "V2",         "type": "input",-        "description": "Digital control voltage 2 (complement of V1). VLOW = 0 to 0.2 V @ 20 \u00b5A max, VHIGH = 3 V @ 100 \u00b5A max to 5 V @ 200 \u00b5A max. When V2 = HIGH and V1 = LOW, J1\u2194J3 is in insertion-loss (through) state."+        "description": "Digital control voltage 2 (complement of V1). VLOW = 0 to 0.2 V @ 20 µA max, VHIGH = 3 V @ 100 µA max to 5 V @ 200 µA max. When V2 = HIGH and V1 = LOW, J1↔J3 is in insertion-loss (through) state."       }     ],     "provenance": {@@ -126,5 +126,8 @@     "docs/as169-73lf-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ]+  ],+  "visibility": {+    "public": true+  } }\ No newline at end of file