apm32e103ret6

@@ -0,0 +1,111 @@+# APM32E103RET6++**Geehy** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)++APM32E103RET6 from Geehy, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VBAT | power_in | Backup domain power supply, 1.8-3.6 V. Powers RTC, LSE oscillator and backup registers when VDD is absent. |+| 2 | PC13-TAMPER-RTC | bidirectional | Port C bit 13. Muxed with TAMPER_RTC alternate function. Supplied via backup switch: max 3 mA sink, only one of PC13/14/15 may be an output at a time, limited to 2 MHz mode and 30 pF load. |+| 3 | PC14-OSC32_IN | bidirectional | Port C bit 14. Default function is 32.768 kHz LSE crystal input (OSC32_IN). Same backup-domain drive limits as PC13. |+| 4 | PC15-OSC32_OUT | bidirectional | Port C bit 15. Default function is 32.768 kHz LSE crystal output (OSC32_OUT). Same backup-domain drive limits as PC13. |+| 5 | PD0-OSC_IN | bidirectional | After reset defaults to HSE crystal input OSC_IN; can be remapped by software to GPIO PD0. Output mode limited to 50 MHz. |+| 6 | PD1-OSC_OUT | bidirectional | After reset defaults to HSE crystal output OSC_OUT; can be remapped by software to GPIO PD1. Output mode limited to 50 MHz. |+| 7 | NRST | bidirectional | Bidirectional reset input/output with internal weak pull-up. Active-low system reset. |+| 8 | PC0 | bidirectional | Port C bit 0. 3.3 V standard I/O with direct ADC connection. Alt: ADC123_IN10. |+| 9 | PC1 | bidirectional | Port C bit 1. 3.3 V standard I/O with direct ADC connection. Alt: ADC123_IN11. |+| 10 | PC2 | bidirectional | Port C bit 2. 3.3 V standard I/O with direct ADC connection. Alt: ADC123_IN12. |+| 11 | PC3 | bidirectional | Port C bit 3. 3.3 V standard I/O with direct ADC connection. Alt: ADC123_IN13. |+| 12 | VSSA | power_in | Analog ground reference for ADC and DAC. |+| 13 | VDDA | power_in | Analog supply, 2.0-3.6 V. Supplies ADC, DAC, reset block and PLL. Must be tied to VDD if not used separately. |+| 14 | PA0-WKUP | bidirectional | Port A bit 0. Standby wake-up input. Alt: USART2_CTS, ADC123_IN0, TMR2_CH1_ETR, TMR5_CH1, TMR8_ETR. |+| 15 | PA1 | bidirectional | Port A bit 1. Alt: USART2_RTS, ADC123_IN1, TMR5_CH2, TMR2_CH2. |+| 16 | PA2 | bidirectional | Port A bit 2. Alt: USART2_TX, TMR5_CH3, ADC123_IN2, TMR2_CH3. |+| 17 | PA3 | bidirectional | Port A bit 3. Alt: USART2_RX, TMR5_CH4, ADC123_IN3, TMR2_CH4. |+| 18 | VSS_4 | power_in | Digital ground pin (bank 4). Tie to system ground. |+| 19 | VDD_4 | power_in | Digital supply pin (bank 4), 2.0-3.6 V. Decouple with local 100 nF to VSS_4. |+| 20 | PA4 | bidirectional | Port A bit 4. Alt: SPI1_NSS, USART2_CK, DAC_OUT1, ADC12_IN4. |+| 21 | PA5 | bidirectional | Port A bit 5. Alt: SPI1_SCK, DAC_OUT2, ADC12_IN5. |+| 22 | PA6 | bidirectional | Port A bit 6. Alt: SPI1_MISO, TMR8_BKIN, ADC12_IN6; remap TMR3_CH1, TMR1_BKIN. |+| 23 | PA7 | bidirectional | Port A bit 7. Alt: SPI1_MOSI, TMR8_CH1N, ADC12_IN7, TMR3_CH2; remap TMR1_CH1N. |+| 24 | PC4 | bidirectional | Port C bit 4. Alt: ADC12_IN14. |+| 25 | PC5 | bidirectional | Port C bit 5. Alt: ADC12_IN15. |+| 26 | PB0 | bidirectional | Port B bit 0. Alt: ADC12_IN8, TMR3_CH3, TMR8_CH2N; remap TMR1_CH2N. |+| 27 | PB1 | bidirectional | Port B bit 1. Alt: ADC12_IN9, TMR3_CH4, TMR8_CH3N; remap TMR1_CH3N. |+| 28 | PB2 | bidirectional | Port B bit 2 (also BOOT1 strap). 5 V-tolerant. Latched at reset as BOOT1 to select boot mode; otherwise a general GPIO. |+| 29 | PB10 | bidirectional | Port B bit 10. Alt: I2C2_SCL, USART3_TX, DMC_UDQM; remap TMR2_CH3. |+| 30 | PB11 | bidirectional | Port B bit 11. Alt: I2C2_SDA, USART3_RX, CKE; remap TMR2_CH4. |+| 31 | VSS_1 | power_in | Digital ground pin (bank 1). Tie to system ground. |+| 32 | VDD_1 | power_in | Digital supply pin (bank 1), 2.0-3.6 V. Decouple with local 100 nF to VSS_1. |+| 33 | PB12 | bidirectional | Port B bit 12. Alt: SPI2_NSS, I2S2_WS, I2C2_SMBAI, USART3_CK, TMR1_BKIN, CAN2_RX. |+| 34 | PB13 | bidirectional | Port B bit 13. Alt: SPI2_SCK, I2S2_CK, USART3_CTS, TMR1_CH1N, CAN2_TX. |+| 35 | PB14 | bidirectional | Port B bit 14. Alt: SPI2_MISO, TMR1_CH2N, USART3_RTS. |+| 36 | PB15 | bidirectional | Port B bit 15. Alt: SPI2_MOSI, I2S2_SD, TMR1_CH3N. |+| 37 | PC6 | bidirectional | Port C bit 6. Alt: I2S2_MCK, TMR8_CH1, SDIO_D6; remap TMR3_CH1. |+| 38 | PC7 | bidirectional | Port C bit 7. Alt: I2S3_MCK, TMR8_CH2, SDIO_D7; remap TMR3_CH2. |+| 39 | PC8 | bidirectional | Port C bit 8. Alt: TMR8_CH3, SDIO_D0; remap TMR3_CH3. |+| 40 | PC9 | bidirectional | Port C bit 9. Alt: TMR8_CH4, SDIO_D1; remap TMR3_CH4. |+| 41 | PA8 | bidirectional | Port A bit 8. Alt: USART1_CK, TMR1_CH1, MCO (master clock output). |+| 42 | PA9 | bidirectional | Port A bit 9. Alt: USART1_TX, TMR1_CH2. |+| 43 | PA10 | bidirectional | Port A bit 10. Alt: USART1_RX, TMR1_CH3. |+| 44 | PA11 | bidirectional | Port A bit 11. Alt: USART1_CTS, USBDDM, USBD2DM, CAN1_RX, TMR1_CH4. |+| 45 | PA12 | bidirectional | Port A bit 12. Alt: USART1_RTS, USBDDP, USBD2DP, CAN1_TX, TMR1_ETR. |+| 46 | PA13 | bidirectional | Port A bit 13. After reset defaults to JTMS/SWDIO debug function; can be re-assigned to GPIO PA13. |+| 47 | VSS_2 | power_in | Digital ground pin (bank 2). Tie to system ground. |+| 48 | VDD_2 | power_in | Digital supply pin (bank 2), 2.0-3.6 V. Decouple with local 100 nF to VSS_2. |+| 49 | PA14 | bidirectional | Port A bit 14. After reset defaults to JTCK/SWCLK debug function; can be re-assigned to GPIO PA14. |+| 50 | PA15 | bidirectional | Port A bit 15. After reset defaults to JTDI. Alt: SPI3_NSS, I2S3_WS; remap TMR2_CH1_ETR, PA15, SPI1_NSS. |+| 51 | PC10 | bidirectional | Port C bit 10. Alt: UART4_TX, SDIO_D2, DMC_DQ8; remap USART3_TX. |+| 52 | PC11 | bidirectional | Port C bit 11. Alt: UART4_RX, SDIO_D3, DMC_DQ9; remap USART3_RX. |+| 53 | PC12 | bidirectional | Port C bit 12. Alt: UART5_TX, SDIO_CK; remap USART3_CK. |+| 54 | PD2 | bidirectional | Port D bit 2. Alt: TMR3_ETR, UART5_RX, SDIO_CMD, DMC_DQ10. |+| 55 | PB3 | bidirectional | Port B bit 3. After reset defaults to JTDO. Alt: SPI3_SCK, I2S3_CK; remap TRACESWO, TMR2_CH2, SPI1_SCK, PB3. |+| 56 | PB4 | bidirectional | Port B bit 4. After reset defaults to NJTRST. Alt: SPI3_MISO; remap TMR3_CH1, SPI1_MISO, PB4. |+| 57 | PB5 | bidirectional | Port B bit 5. 3.3 V standard I/O. Alt: I2C1_SMBAI, SPI3_MOSI, I2S3_SD; remap TMR3_CH2, SPI1_MOSI, CAN2_RX. |+| 58 | PB6 | bidirectional | Port B bit 6. Alt: I2C1_SCL, I2C3_SCL, TMR4_CH1; remap USART1_TX, CAN2_TX. |+| 59 | PB7 | bidirectional | Port B bit 7. Alt: I2C1_SDA, I2C3_SDA, SMC_NADV, TMR4_CH2; remap USART1_RX. |+| 60 | BOOT0 | input | Boot mode select input. Latched at reset together with BOOT1 (PB2) to select boot from Flash, System Memory or SRAM. |+| 61 | PB8 | bidirectional | Port B bit 8. Alt: TMR4_CH3, SDIO_D4; remap I2C1_SCL, I2C3_SCL, CAN1_RX. |+| 62 | PB9 | bidirectional | Port B bit 9. Alt: TMR4_CH4, SDIO_D5; remap I2C1_SDA, I2C3_SDA, CAN1_TX. |+| 63 | VSS_3 | power_in | Digital ground pin (bank 3). Tie to system ground. |+| 64 | VDD_3 | power_in | Digital supply pin (bank 3), 2.0-3.6 V. Decouple with local 100 nF to VSS_3. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Geehy |+| Package | LQFP-64(10x10) |+| Category | MCU |+| Pins | 64 |++## Ordering variants++- `APM32E103RET6CC (256KB Flash)`+- `APM32E103RET6CE (512KB Flash)`+- `APM32E103RET6RC (256KB Flash)`+- `APM32E103RET6RE (512KB Flash / this part, RET6)`+- `APM32E103RET6VC (256KB Flash)`+- `APM32E103RET6VE (512KB Flash)`+- `APM32E103RET6ZC (256KB Flash)`+- `APM32E103RET6ZE (512KB Flash)`++## CAD (KiCad official)++- Symbol: `APM32E103RET6`+- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`+- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Geehy datasheet](docs/apm32e103ret6-datasheet.pdf) (None pp, sha256 `c83e8dd35e2b9455`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/apm32e103ret6-datasheet.pdf)